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648 lines
15 KiB
648 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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Madge Ambassador ATM Adapter driver. |
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Copyright (C) 1995-1999 Madge Networks Ltd. |
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*/ |
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#ifndef AMBASSADOR_H |
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#define AMBASSADOR_H |
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#ifdef CONFIG_ATM_AMBASSADOR_DEBUG |
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#define DEBUG_AMBASSADOR |
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#endif |
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#define DEV_LABEL "amb" |
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#ifndef PCI_VENDOR_ID_MADGE |
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#define PCI_VENDOR_ID_MADGE 0x10B6 |
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#endif |
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#ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR |
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#define PCI_DEVICE_ID_MADGE_AMBASSADOR 0x1001 |
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#endif |
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#ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD |
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#define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002 |
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#endif |
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// diagnostic output |
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#define PRINTK(severity,format,args...) \ |
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printk(severity DEV_LABEL ": " format "\n" , ## args) |
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#ifdef DEBUG_AMBASSADOR |
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#define DBG_ERR 0x0001 |
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#define DBG_WARN 0x0002 |
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#define DBG_INFO 0x0004 |
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#define DBG_INIT 0x0008 |
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#define DBG_LOAD 0x0010 |
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#define DBG_VCC 0x0020 |
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#define DBG_QOS 0x0040 |
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#define DBG_CMD 0x0080 |
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#define DBG_TX 0x0100 |
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#define DBG_RX 0x0200 |
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#define DBG_SKB 0x0400 |
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#define DBG_POOL 0x0800 |
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#define DBG_IRQ 0x1000 |
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#define DBG_FLOW 0x2000 |
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#define DBG_REGS 0x4000 |
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#define DBG_DATA 0x8000 |
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#define DBG_MASK 0xffff |
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/* the ## prevents the annoying double expansion of the macro arguments */ |
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/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */ |
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#define PRINTDB(bits,format,args...) \ |
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( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 ) |
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#define PRINTDM(bits,format,args...) \ |
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( (debug & (bits)) ? printk (format , ## args) : 1 ) |
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#define PRINTDE(bits,format,args...) \ |
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( (debug & (bits)) ? printk (format "\n" , ## args) : 1 ) |
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#define PRINTD(bits,format,args...) \ |
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( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 ) |
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#else |
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#define PRINTD(bits,format,args...) |
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#define PRINTDB(bits,format,args...) |
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#define PRINTDM(bits,format,args...) |
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#define PRINTDE(bits,format,args...) |
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#endif |
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#define PRINTDD(bits,format,args...) |
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#define PRINTDDB(sec,fmt,args...) |
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#define PRINTDDM(sec,fmt,args...) |
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#define PRINTDDE(sec,fmt,args...) |
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// tunable values (?) |
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/* MUST be powers of two -- why ? */ |
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#define COM_Q_ENTRIES 8 |
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#define TX_Q_ENTRIES 32 |
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#define RX_Q_ENTRIES 64 |
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// fixed values |
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// guessing |
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#define AMB_EXTENT 0x80 |
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// Minimum allowed size for an Ambassador queue |
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#define MIN_QUEUE_SIZE 2 |
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// Ambassador microcode allows 1 to 4 pools, we use 4 (simpler) |
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#define NUM_RX_POOLS 4 |
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// minimum RX buffers required to cope with replenishing delay |
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#define MIN_RX_BUFFERS 1 |
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// minimum PCI latency we will tolerate (32 IS TOO SMALL) |
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#define MIN_PCI_LATENCY 64 // 255 |
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// VCs supported by card (VPI always 0) |
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#define NUM_VPI_BITS 0 |
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#define NUM_VCI_BITS 10 |
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#define NUM_VCS 1024 |
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/* The status field bits defined so far. */ |
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#define RX_ERR 0x8000 // always present if there is an error (hmm) |
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#define CRC_ERR 0x4000 // AAL5 CRC error |
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#define LEN_ERR 0x2000 // overlength frame |
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#define ABORT_ERR 0x1000 // zero length field in received frame |
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#define UNUSED_ERR 0x0800 // buffer returned unused |
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// Adaptor commands |
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#define SRB_OPEN_VC 0 |
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/* par_0: dwordswap(VC_number) */ |
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/* par_1: dwordswap(flags<<16) or wordswap(flags)*/ |
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/* flags: */ |
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/* LANE: 0x0004 */ |
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/* NOT_UBR: 0x0008 */ |
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/* ABR: 0x0010 */ |
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/* RxPool0: 0x0000 */ |
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/* RxPool1: 0x0020 */ |
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/* RxPool2: 0x0040 */ |
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/* RxPool3: 0x0060 */ |
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/* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */ |
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#define SRB_CLOSE_VC 1 |
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/* par_0: dwordswap(VC_number) */ |
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#define SRB_GET_BIA 2 |
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/* returns */ |
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/* par_0: dwordswap(half BIA) */ |
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/* par_1: dwordswap(half BIA) */ |
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#define SRB_GET_SUNI_STATS 3 |
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/* par_0: dwordswap(physical_host_address) */ |
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#define SRB_SET_BITS_8 4 |
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#define SRB_SET_BITS_16 5 |
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#define SRB_SET_BITS_32 6 |
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#define SRB_CLEAR_BITS_8 7 |
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#define SRB_CLEAR_BITS_16 8 |
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#define SRB_CLEAR_BITS_32 9 |
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/* par_0: dwordswap(ATMizer address) */ |
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/* par_1: dwordswap(mask) */ |
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#define SRB_SET_8 10 |
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#define SRB_SET_16 11 |
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#define SRB_SET_32 12 |
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/* par_0: dwordswap(ATMizer address) */ |
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/* par_1: dwordswap(data) */ |
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#define SRB_GET_32 13 |
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/* par_0: dwordswap(ATMizer address) */ |
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/* returns */ |
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/* par_1: dwordswap(ATMizer data) */ |
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#define SRB_GET_VERSION 14 |
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/* returns */ |
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/* par_0: dwordswap(Major Version) */ |
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/* par_1: dwordswap(Minor Version) */ |
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#define SRB_FLUSH_BUFFER_Q 15 |
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/* Only flags to define which buffer pool; all others must be zero */ |
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/* par_0: dwordswap(flags<<16) or wordswap(flags)*/ |
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#define SRB_GET_DMA_SPEEDS 16 |
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/* returns */ |
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/* par_0: dwordswap(Read speed (bytes/sec)) */ |
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/* par_1: dwordswap(Write speed (bytes/sec)) */ |
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#define SRB_MODIFY_VC_RATE 17 |
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/* par_0: dwordswap(VC_number) */ |
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/* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */ |
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#define SRB_MODIFY_VC_FLAGS 18 |
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/* par_0: dwordswap(VC_number) */ |
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/* par_1: dwordswap(flags<<16) or wordswap(flags)*/ |
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/* flags: */ |
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/* LANE: 0x0004 */ |
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/* NOT_UBR: 0x0008 */ |
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/* ABR: 0x0010 */ |
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/* RxPool0: 0x0000 */ |
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/* RxPool1: 0x0020 */ |
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/* RxPool2: 0x0040 */ |
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/* RxPool3: 0x0060 */ |
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#define SRB_RATE_SHIFT 16 |
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#define SRB_POOL_SHIFT (SRB_FLAGS_SHIFT+5) |
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#define SRB_FLAGS_SHIFT 16 |
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#define SRB_STOP_TASKING 19 |
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#define SRB_START_TASKING 20 |
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#define SRB_SHUT_DOWN 21 |
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#define MAX_SRB 21 |
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#define SRB_COMPLETE 0xffffffff |
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#define TX_FRAME 0x80000000 |
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// number of types of SRB MUST be a power of two -- why? |
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#define NUM_OF_SRB 32 |
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// number of bits of period info for rate |
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#define MAX_RATE_BITS 6 |
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#define TX_UBR 0x0000 |
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#define TX_UBR_CAPPED 0x0008 |
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#define TX_ABR 0x0018 |
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#define TX_FRAME_NOTCAP 0x0000 |
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#define TX_FRAME_CAPPED 0x8000 |
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#define FP_155_RATE 0x24b1 |
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#define FP_25_RATE 0x1f9d |
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/* #define VERSION_NUMBER 0x01000000 // initial release */ |
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/* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */ |
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/* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */ |
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/* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */ |
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/* #define VERSION_NUMBER 0x01040000 // PLX bug work around version PLUS */ |
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/* remove race conditions on basic interface */ |
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/* indicate to the host that diagnostics */ |
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/* have finished; if failed, how and what */ |
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/* failed */ |
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/* fix host memory test to fix PLX bug */ |
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/* allow flash upgrade and BIA upgrade directly */ |
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/* */ |
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#define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */ |
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/* Change in download algorithm */ |
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#define DMA_VALID 0xb728e149 /* completely random */ |
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#define FLASH_BASE 0xa0c00000 |
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#define FLASH_SIZE 0x00020000 /* 128K */ |
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#define BIA_BASE (FLASH_BASE+0x0001c000) /* Flash Sector 7 */ |
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#define BIA_ADDRESS ((void *)0xa0c1c000) |
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#define PLX_BASE 0xe0000000 |
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typedef enum { |
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host_memory_test = 1, |
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read_adapter_memory, |
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write_adapter_memory, |
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adapter_start, |
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get_version_number, |
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interrupt_host, |
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flash_erase_sector, |
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adap_download_block = 0x20, |
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adap_erase_flash, |
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adap_run_in_iram, |
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adap_end_download |
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} loader_command; |
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#define BAD_COMMAND (-1) |
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#define COMMAND_IN_PROGRESS 1 |
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#define COMMAND_PASSED_TEST 2 |
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#define COMMAND_FAILED_TEST 3 |
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#define COMMAND_READ_DATA_OK 4 |
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#define COMMAND_READ_BAD_ADDRESS 5 |
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#define COMMAND_WRITE_DATA_OK 6 |
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#define COMMAND_WRITE_BAD_ADDRESS 7 |
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#define COMMAND_WRITE_FLASH_FAILURE 8 |
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#define COMMAND_COMPLETE 9 |
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#define COMMAND_FLASH_ERASE_FAILURE 10 |
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#define COMMAND_WRITE_BAD_DATA 11 |
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/* bit fields for mailbox[0] return values */ |
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#define GPINT_TST_FAILURE 0x00000001 |
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#define SUNI_DATA_PATTERN_FAILURE 0x00000002 |
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#define SUNI_DATA_BITS_FAILURE 0x00000004 |
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#define SUNI_UTOPIA_FAILURE 0x00000008 |
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#define SUNI_FIFO_FAILURE 0x00000010 |
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#define SRAM_FAILURE 0x00000020 |
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#define SELF_TEST_FAILURE 0x0000003f |
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/* mailbox[1] = 0 in progress, -1 on completion */ |
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/* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */ |
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/* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */ |
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/* mailbox[4],mailbox[5],mailbox[6] random failure values */ |
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/* PLX/etc. memory map including command structure */ |
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/* These registers may also be memory mapped in PCI memory */ |
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#define UNUSED_LOADER_MAILBOXES 6 |
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typedef struct { |
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u32 stuff[16]; |
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union { |
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struct { |
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u32 result; |
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u32 ready; |
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u32 stuff[UNUSED_LOADER_MAILBOXES]; |
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} loader; |
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struct { |
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u32 cmd_address; |
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u32 tx_address; |
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u32 rx_address[NUM_RX_POOLS]; |
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u32 gen_counter; |
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u32 spare; |
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} adapter; |
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} mb; |
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u32 doorbell; |
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u32 interrupt; |
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u32 interrupt_control; |
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u32 reset_control; |
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} amb_mem; |
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/* RESET bit, IRQ (card to host) and doorbell (host to card) enable bits */ |
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#define AMB_RESET_BITS 0x40000000 |
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#define AMB_INTERRUPT_BITS 0x00000300 |
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#define AMB_DOORBELL_BITS 0x00030000 |
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/* loader commands */ |
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#define MAX_COMMAND_DATA 13 |
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#define MAX_TRANSFER_DATA 11 |
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typedef struct { |
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__be32 address; |
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__be32 count; |
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__be32 data[MAX_TRANSFER_DATA]; |
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} transfer_block; |
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typedef struct { |
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__be32 result; |
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__be32 command; |
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union { |
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transfer_block transfer; |
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__be32 version; |
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__be32 start; |
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__be32 data[MAX_COMMAND_DATA]; |
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} payload; |
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__be32 valid; |
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} loader_block; |
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/* command queue */ |
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/* Again all data are BIG ENDIAN */ |
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typedef struct { |
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union { |
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struct { |
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__be32 vc; |
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__be32 flags; |
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__be32 rate; |
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} open; |
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struct { |
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__be32 vc; |
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__be32 rate; |
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} modify_rate; |
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struct { |
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__be32 vc; |
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__be32 flags; |
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} modify_flags; |
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struct { |
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__be32 vc; |
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} close; |
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struct { |
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__be32 lower4; |
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__be32 upper2; |
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} bia; |
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struct { |
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__be32 address; |
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} suni; |
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struct { |
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__be32 major; |
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__be32 minor; |
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} version; |
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struct { |
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__be32 read; |
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__be32 write; |
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} speed; |
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struct { |
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__be32 flags; |
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} flush; |
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struct { |
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__be32 address; |
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__be32 data; |
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} memory; |
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__be32 par[3]; |
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} args; |
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__be32 request; |
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} command; |
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/* transmit queues and associated structures */ |
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/* The hosts transmit structure. All BIG ENDIAN; host address |
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restricted to first 1GByte, but address passed to the card must |
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have the top MS bit or'ed in. -- check this */ |
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/* TX is described by 1+ tx_frags followed by a tx_frag_end */ |
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typedef struct { |
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__be32 bytes; |
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__be32 address; |
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} tx_frag; |
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/* apart from handle the fields here are for the adapter to play with |
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and should be set to zero */ |
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typedef struct { |
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u32 handle; |
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u16 vc; |
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u16 next_descriptor_length; |
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u32 next_descriptor; |
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#ifdef AMB_NEW_MICROCODE |
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u8 cpcs_uu; |
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u8 cpi; |
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u16 pad; |
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#endif |
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} tx_frag_end; |
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typedef struct { |
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tx_frag tx_frag; |
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tx_frag_end tx_frag_end; |
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struct sk_buff * skb; |
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} tx_simple; |
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#if 0 |
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typedef union { |
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tx_frag fragment; |
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tx_frag_end end_of_list; |
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} tx_descr; |
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#endif |
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/* this "points" to the sequence of fragments and trailer */ |
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typedef struct { |
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__be16 vc; |
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__be16 tx_descr_length; |
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__be32 tx_descr_addr; |
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} tx_in; |
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/* handle is the handle from tx_in */ |
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typedef struct { |
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u32 handle; |
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} tx_out; |
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/* receive frame structure */ |
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/* All BIG ENDIAN; handle is as passed from host; length is zero for |
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aborted frames, and frames with errors. Header is actually VC |
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number, lec-id is NOT yet supported. */ |
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typedef struct { |
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u32 handle; |
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__be16 vc; |
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__be16 lec_id; // unused |
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__be16 status; |
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__be16 length; |
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} rx_out; |
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/* buffer supply structure */ |
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typedef struct { |
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u32 handle; |
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__be32 host_address; |
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} rx_in; |
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/* This first structure is the area in host memory where the adapter |
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writes its pointer values. These pointer values are BIG ENDIAN and |
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reside in the same 4MB 'page' as this structure. The host gives the |
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adapter the address of this block by sending a doorbell interrupt |
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to the adapter after downloading the code and setting it going. The |
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addresses have the top 10 bits set to 1010000010b -- really? |
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The host must initialise these before handing the block to the |
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adapter. */ |
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typedef struct { |
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__be32 command_start; /* SRB commands completions */ |
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__be32 command_end; /* SRB commands completions */ |
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__be32 tx_start; |
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__be32 tx_end; |
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__be32 txcom_start; /* tx completions */ |
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__be32 txcom_end; /* tx completions */ |
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struct { |
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__be32 buffer_start; |
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__be32 buffer_end; |
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u32 buffer_q_get; |
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u32 buffer_q_end; |
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u32 buffer_aptr; |
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__be32 rx_start; /* rx completions */ |
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__be32 rx_end; |
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u32 rx_ptr; |
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__be32 buffer_size; /* size of host buffer */ |
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} rec_struct[NUM_RX_POOLS]; |
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#ifdef AMB_NEW_MICROCODE |
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u16 init_flags; |
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u16 talk_block_spare; |
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#endif |
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} adap_talk_block; |
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/* This structure must be kept in line with the vcr image in sarmain.h |
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This is the structure in the host filled in by the adapter by |
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GET_SUNI_STATS */ |
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typedef struct { |
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u8 racp_chcs; |
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u8 racp_uhcs; |
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u16 spare; |
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u32 racp_rcell; |
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u32 tacp_tcell; |
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u32 flags; |
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u32 dropped_cells; |
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u32 dropped_frames; |
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} suni_stats; |
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typedef enum { |
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dead |
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} amb_flags; |
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#define NEXTQ(current,start,limit) \ |
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( (current)+1 < (limit) ? (current)+1 : (start) ) |
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typedef struct { |
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command * start; |
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command * in; |
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command * out; |
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command * limit; |
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} amb_cq_ptrs; |
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typedef struct { |
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spinlock_t lock; |
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unsigned int pending; |
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unsigned int high; |
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unsigned int filled; |
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unsigned int maximum; // size - 1 (q implementation) |
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amb_cq_ptrs ptrs; |
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} amb_cq; |
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typedef struct { |
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spinlock_t lock; |
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unsigned int pending; |
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unsigned int high; |
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unsigned int filled; |
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unsigned int maximum; // size - 1 (q implementation) |
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struct { |
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tx_in * start; |
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tx_in * ptr; |
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tx_in * limit; |
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} in; |
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struct { |
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tx_out * start; |
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tx_out * ptr; |
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tx_out * limit; |
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} out; |
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} amb_txq; |
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typedef struct { |
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spinlock_t lock; |
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unsigned int pending; |
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unsigned int low; |
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unsigned int emptied; |
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unsigned int maximum; // size - 1 (q implementation) |
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struct { |
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rx_in * start; |
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rx_in * ptr; |
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rx_in * limit; |
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} in; |
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struct { |
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rx_out * start; |
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rx_out * ptr; |
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rx_out * limit; |
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} out; |
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unsigned int buffers_wanted; |
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unsigned int buffer_size; |
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} amb_rxq; |
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typedef struct { |
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unsigned long tx_ok; |
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struct { |
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unsigned long ok; |
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unsigned long error; |
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unsigned long badcrc; |
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unsigned long toolong; |
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unsigned long aborted; |
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unsigned long unused; |
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} rx; |
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} amb_stats; |
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// a single struct pointed to by atm_vcc->dev_data |
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typedef struct { |
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u8 tx_vc_bits:7; |
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u8 tx_present:1; |
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} amb_tx_info; |
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typedef struct { |
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unsigned char pool; |
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} amb_rx_info; |
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typedef struct { |
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amb_rx_info rx_info; |
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u16 tx_frame_bits; |
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unsigned int tx_rate; |
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unsigned int rx_rate; |
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} amb_vcc; |
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struct amb_dev { |
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u8 irq; |
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unsigned long flags; |
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u32 iobase; |
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u32 * membase; |
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amb_cq cq; |
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amb_txq txq; |
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amb_rxq rxq[NUM_RX_POOLS]; |
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struct mutex vcc_sf; |
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amb_tx_info txer[NUM_VCS]; |
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struct atm_vcc * rxer[NUM_VCS]; |
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unsigned int tx_avail; |
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unsigned int rx_avail; |
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amb_stats stats; |
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struct atm_dev * atm_dev; |
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struct pci_dev * pci_dev; |
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struct timer_list housekeeping; |
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}; |
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typedef struct amb_dev amb_dev; |
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#define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data) |
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#define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data) |
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/* rate rounding */ |
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typedef enum { |
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round_up, |
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round_down, |
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round_nearest |
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} rounding; |
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#endif
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