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424 lines
11 KiB
424 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA |
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* |
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* Maintained by: Jeremy Higdon @ SGI |
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* Please ALWAYS copy [email protected] |
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* on emails. |
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* |
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* Copyright 2004 SGI |
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* |
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* Bits from Jeff Garzik, Copyright RedHat, Inc. |
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* |
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* libata documentation is available via 'make {ps|pdf}docs', |
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* as Documentation/driver-api/libata.rst |
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* |
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* Vitesse hardware documentation presumably available under NDA. |
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* Intel 31244 (same hardware interface) documentation presumably |
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* available from http://developer.intel.com/ |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/device.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#define DRV_NAME "sata_vsc" |
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#define DRV_VERSION "2.3" |
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enum { |
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VSC_MMIO_BAR = 0, |
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/* Interrupt register offsets (from chip base address) */ |
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VSC_SATA_INT_STAT_OFFSET = 0x00, |
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VSC_SATA_INT_MASK_OFFSET = 0x04, |
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/* Taskfile registers offsets */ |
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VSC_SATA_TF_CMD_OFFSET = 0x00, |
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VSC_SATA_TF_DATA_OFFSET = 0x00, |
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VSC_SATA_TF_ERROR_OFFSET = 0x04, |
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VSC_SATA_TF_FEATURE_OFFSET = 0x06, |
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VSC_SATA_TF_NSECT_OFFSET = 0x08, |
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VSC_SATA_TF_LBAL_OFFSET = 0x0c, |
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VSC_SATA_TF_LBAM_OFFSET = 0x10, |
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VSC_SATA_TF_LBAH_OFFSET = 0x14, |
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VSC_SATA_TF_DEVICE_OFFSET = 0x18, |
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VSC_SATA_TF_STATUS_OFFSET = 0x1c, |
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VSC_SATA_TF_COMMAND_OFFSET = 0x1d, |
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VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28, |
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VSC_SATA_TF_CTL_OFFSET = 0x29, |
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/* DMA base */ |
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VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64, |
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VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C, |
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VSC_SATA_DMA_CMD_OFFSET = 0x70, |
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/* SCRs base */ |
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VSC_SATA_SCR_STATUS_OFFSET = 0x100, |
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VSC_SATA_SCR_ERROR_OFFSET = 0x104, |
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VSC_SATA_SCR_CONTROL_OFFSET = 0x108, |
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/* Port stride */ |
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VSC_SATA_PORT_OFFSET = 0x200, |
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/* Error interrupt status bit offsets */ |
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VSC_SATA_INT_ERROR_CRC = 0x40, |
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VSC_SATA_INT_ERROR_T = 0x20, |
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VSC_SATA_INT_ERROR_P = 0x10, |
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VSC_SATA_INT_ERROR_R = 0x8, |
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VSC_SATA_INT_ERROR_E = 0x4, |
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VSC_SATA_INT_ERROR_M = 0x2, |
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VSC_SATA_INT_PHY_CHANGE = 0x1, |
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VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \ |
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VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \ |
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VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \ |
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VSC_SATA_INT_PHY_CHANGE), |
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}; |
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static int vsc_sata_scr_read(struct ata_link *link, |
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unsigned int sc_reg, u32 *val) |
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{ |
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if (sc_reg > SCR_CONTROL) |
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return -EINVAL; |
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*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
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return 0; |
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} |
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static int vsc_sata_scr_write(struct ata_link *link, |
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unsigned int sc_reg, u32 val) |
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{ |
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if (sc_reg > SCR_CONTROL) |
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return -EINVAL; |
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writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
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return 0; |
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} |
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static void vsc_freeze(struct ata_port *ap) |
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{ |
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void __iomem *mask_addr; |
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mask_addr = ap->host->iomap[VSC_MMIO_BAR] + |
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VSC_SATA_INT_MASK_OFFSET + ap->port_no; |
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writeb(0, mask_addr); |
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} |
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static void vsc_thaw(struct ata_port *ap) |
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{ |
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void __iomem *mask_addr; |
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mask_addr = ap->host->iomap[VSC_MMIO_BAR] + |
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VSC_SATA_INT_MASK_OFFSET + ap->port_no; |
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writeb(0xff, mask_addr); |
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} |
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static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl) |
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{ |
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void __iomem *mask_addr; |
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u8 mask; |
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mask_addr = ap->host->iomap[VSC_MMIO_BAR] + |
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VSC_SATA_INT_MASK_OFFSET + ap->port_no; |
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mask = readb(mask_addr); |
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if (ctl & ATA_NIEN) |
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mask |= 0x80; |
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else |
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mask &= 0x7F; |
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writeb(mask, mask_addr); |
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} |
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static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
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{ |
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struct ata_ioports *ioaddr = &ap->ioaddr; |
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
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/* |
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* The only thing the ctl register is used for is SRST. |
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* That is not enabled or disabled via tf_load. |
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* However, if ATA_NIEN is changed, then we need to change |
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* the interrupt register. |
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*/ |
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if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) { |
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ap->last_ctl = tf->ctl; |
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vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN); |
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} |
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
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writew(tf->feature | (((u16)tf->hob_feature) << 8), |
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ioaddr->feature_addr); |
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writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
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ioaddr->nsect_addr); |
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writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
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ioaddr->lbal_addr); |
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writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
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ioaddr->lbam_addr); |
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writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
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ioaddr->lbah_addr); |
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} else if (is_addr) { |
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writew(tf->feature, ioaddr->feature_addr); |
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writew(tf->nsect, ioaddr->nsect_addr); |
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writew(tf->lbal, ioaddr->lbal_addr); |
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writew(tf->lbam, ioaddr->lbam_addr); |
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writew(tf->lbah, ioaddr->lbah_addr); |
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} |
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if (tf->flags & ATA_TFLAG_DEVICE) |
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writeb(tf->device, ioaddr->device_addr); |
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ata_wait_idle(ap); |
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} |
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static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
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{ |
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struct ata_ioports *ioaddr = &ap->ioaddr; |
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u16 nsect, lbal, lbam, lbah, feature; |
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tf->command = ata_sff_check_status(ap); |
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tf->device = readw(ioaddr->device_addr); |
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feature = readw(ioaddr->error_addr); |
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nsect = readw(ioaddr->nsect_addr); |
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lbal = readw(ioaddr->lbal_addr); |
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lbam = readw(ioaddr->lbam_addr); |
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lbah = readw(ioaddr->lbah_addr); |
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tf->feature = feature; |
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tf->nsect = nsect; |
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tf->lbal = lbal; |
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tf->lbam = lbam; |
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tf->lbah = lbah; |
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if (tf->flags & ATA_TFLAG_LBA48) { |
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tf->hob_feature = feature >> 8; |
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tf->hob_nsect = nsect >> 8; |
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tf->hob_lbal = lbal >> 8; |
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tf->hob_lbam = lbam >> 8; |
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tf->hob_lbah = lbah >> 8; |
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} |
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} |
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static inline void vsc_error_intr(u8 port_status, struct ata_port *ap) |
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{ |
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if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M)) |
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ata_port_freeze(ap); |
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else |
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ata_port_abort(ap); |
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} |
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static void vsc_port_intr(u8 port_status, struct ata_port *ap) |
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{ |
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struct ata_queued_cmd *qc; |
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int handled = 0; |
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if (unlikely(port_status & VSC_SATA_INT_ERROR)) { |
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vsc_error_intr(port_status, ap); |
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return; |
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} |
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qc = ata_qc_from_tag(ap, ap->link.active_tag); |
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if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING))) |
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handled = ata_bmdma_port_intr(ap, qc); |
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/* We received an interrupt during a polled command, |
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* or some other spurious condition. Interrupt reporting |
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* with this hardware is fairly reliable so it is safe to |
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* simply clear the interrupt |
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*/ |
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if (unlikely(!handled)) |
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ap->ops->sff_check_status(ap); |
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} |
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/* |
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* vsc_sata_interrupt |
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* |
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* Read the interrupt register and process for the devices that have |
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* them pending. |
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*/ |
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static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance) |
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{ |
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struct ata_host *host = dev_instance; |
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unsigned int i; |
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unsigned int handled = 0; |
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u32 status; |
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status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET); |
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if (unlikely(status == 0xffffffff || status == 0)) { |
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if (status) |
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dev_err(host->dev, |
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": IRQ status == 0xffffffff, PCI fault or device removal?\n"); |
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goto out; |
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} |
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spin_lock(&host->lock); |
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for (i = 0; i < host->n_ports; i++) { |
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u8 port_status = (status >> (8 * i)) & 0xff; |
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if (port_status) { |
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vsc_port_intr(port_status, host->ports[i]); |
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handled++; |
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} |
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} |
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spin_unlock(&host->lock); |
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out: |
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return IRQ_RETVAL(handled); |
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} |
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static struct scsi_host_template vsc_sata_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static struct ata_port_operations vsc_sata_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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/* The IRQ handling is not quite standard SFF behaviour so we |
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cannot use the default lost interrupt handler */ |
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.lost_interrupt = ATA_OP_NULL, |
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.sff_tf_load = vsc_sata_tf_load, |
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.sff_tf_read = vsc_sata_tf_read, |
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.freeze = vsc_freeze, |
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.thaw = vsc_thaw, |
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.scr_read = vsc_sata_scr_read, |
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.scr_write = vsc_sata_scr_write, |
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}; |
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static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
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{ |
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port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; |
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port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; |
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port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET; |
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port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET; |
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port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET; |
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port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET; |
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port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET; |
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port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET; |
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port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET; |
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port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET; |
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port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET; |
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port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET; |
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port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET; |
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port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET; |
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port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET; |
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writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET); |
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writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET); |
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} |
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static int vsc_sata_init_one(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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static const struct ata_port_info pi = { |
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.flags = ATA_FLAG_SATA, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &vsc_sata_ops, |
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}; |
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const struct ata_port_info *ppi[] = { &pi, NULL }; |
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struct ata_host *host; |
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void __iomem *mmio_base; |
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int i, rc; |
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u8 cls; |
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ata_print_version_once(&pdev->dev, DRV_VERSION); |
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/* allocate host */ |
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host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4); |
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if (!host) |
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return -ENOMEM; |
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rc = pcim_enable_device(pdev); |
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if (rc) |
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return rc; |
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/* check if we have needed resource mapped */ |
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if (pci_resource_len(pdev, 0) == 0) |
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return -ENODEV; |
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/* map IO regions and initialize host accordingly */ |
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rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME); |
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if (rc == -EBUSY) |
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pcim_pin_device(pdev); |
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if (rc) |
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return rc; |
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host->iomap = pcim_iomap_table(pdev); |
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mmio_base = host->iomap[VSC_MMIO_BAR]; |
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for (i = 0; i < host->n_ports; i++) { |
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struct ata_port *ap = host->ports[i]; |
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unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET; |
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vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset); |
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ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio"); |
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ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port"); |
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} |
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/* |
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* Use 32 bit DMA mask, because 64 bit address support is poor. |
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*/ |
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rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
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if (rc) |
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return rc; |
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/* |
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* Due to a bug in the chip, the default cache line size can't be |
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* used (unless the default is non-zero). |
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*/ |
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls); |
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if (cls == 0x00) |
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80); |
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if (pci_enable_msi(pdev) == 0) |
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pci_intx(pdev, 0); |
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/* |
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* Config offset 0x98 is "Extended Control and Status Register 0" |
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* Default value is (1 << 28). All bits except bit 28 are reserved in |
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* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity. |
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* If bit 28 is clear, each port has its own LED. |
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*/ |
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pci_write_config_dword(pdev, 0x98, 0); |
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pci_set_master(pdev); |
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return ata_host_activate(host, pdev->irq, vsc_sata_interrupt, |
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IRQF_SHARED, &vsc_sata_sht); |
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} |
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static const struct pci_device_id vsc_sata_pci_tbl[] = { |
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{ PCI_VENDOR_ID_VITESSE, 0x7174, |
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PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 }, |
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{ PCI_VENDOR_ID_INTEL, 0x3200, |
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PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 }, |
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{ } /* terminate list */ |
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}; |
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static struct pci_driver vsc_sata_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = vsc_sata_pci_tbl, |
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.probe = vsc_sata_init_one, |
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.remove = ata_pci_remove_one, |
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}; |
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module_pci_driver(vsc_sata_pci_driver); |
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MODULE_AUTHOR("Jeremy Higdon"); |
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MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl); |
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MODULE_VERSION(DRV_VERSION);
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