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777 lines
20 KiB
777 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2018 Intel Corporation. All rights reserved. */ |
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#include <linux/libnvdimm.h> |
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#include <linux/ndctl.h> |
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#include <linux/acpi.h> |
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#include <asm/smp.h> |
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#include "intel.h" |
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#include "nfit.h" |
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static ssize_t firmware_activate_noidle_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev); |
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struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); |
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struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
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return sprintf(buf, "%s\n", acpi_desc->fwa_noidle ? "Y" : "N"); |
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} |
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static ssize_t firmware_activate_noidle_store(struct device *dev, |
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struct device_attribute *attr, const char *buf, size_t size) |
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{ |
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struct nvdimm_bus *nvdimm_bus = to_nvdimm_bus(dev); |
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struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); |
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struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
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ssize_t rc; |
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bool val; |
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rc = kstrtobool(buf, &val); |
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if (rc) |
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return rc; |
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if (val != acpi_desc->fwa_noidle) |
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acpi_desc->fwa_cap = NVDIMM_FWA_CAP_INVALID; |
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acpi_desc->fwa_noidle = val; |
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return size; |
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} |
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DEVICE_ATTR_RW(firmware_activate_noidle); |
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bool intel_fwa_supported(struct nvdimm_bus *nvdimm_bus) |
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{ |
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struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); |
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struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
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unsigned long *mask; |
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if (!test_bit(NVDIMM_BUS_FAMILY_INTEL, &nd_desc->bus_family_mask)) |
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return false; |
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mask = &acpi_desc->family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL]; |
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return *mask == NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK; |
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} |
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static unsigned long intel_security_flags(struct nvdimm *nvdimm, |
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enum nvdimm_passphrase_type ptype) |
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{ |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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unsigned long security_flags = 0; |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_get_security_state cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_command = NVDIMM_INTEL_GET_SECURITY_STATE, |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_out = |
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sizeof(struct nd_intel_get_security_state), |
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.nd_fw_size = |
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sizeof(struct nd_intel_get_security_state), |
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}, |
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}; |
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int rc; |
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if (!test_bit(NVDIMM_INTEL_GET_SECURITY_STATE, &nfit_mem->dsm_mask)) |
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return 0; |
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/* |
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* Short circuit the state retrieval while we are doing overwrite. |
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* The DSM spec states that the security state is indeterminate |
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* until the overwrite DSM completes. |
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*/ |
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if (nvdimm_in_overwrite(nvdimm) && ptype == NVDIMM_USER) |
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return BIT(NVDIMM_SECURITY_OVERWRITE); |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0 || nd_cmd.cmd.status) { |
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pr_err("%s: security state retrieval failed (%d:%#x)\n", |
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nvdimm_name(nvdimm), rc, nd_cmd.cmd.status); |
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return 0; |
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} |
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/* check and see if security is enabled and locked */ |
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if (ptype == NVDIMM_MASTER) { |
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if (nd_cmd.cmd.extended_state & ND_INTEL_SEC_ESTATE_ENABLED) |
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set_bit(NVDIMM_SECURITY_UNLOCKED, &security_flags); |
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else |
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set_bit(NVDIMM_SECURITY_DISABLED, &security_flags); |
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if (nd_cmd.cmd.extended_state & ND_INTEL_SEC_ESTATE_PLIMIT) |
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set_bit(NVDIMM_SECURITY_FROZEN, &security_flags); |
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return security_flags; |
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} |
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_UNSUPPORTED) |
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return 0; |
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_ENABLED) { |
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_FROZEN || |
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nd_cmd.cmd.state & ND_INTEL_SEC_STATE_PLIMIT) |
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set_bit(NVDIMM_SECURITY_FROZEN, &security_flags); |
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_LOCKED) |
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set_bit(NVDIMM_SECURITY_LOCKED, &security_flags); |
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else |
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set_bit(NVDIMM_SECURITY_UNLOCKED, &security_flags); |
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} else |
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set_bit(NVDIMM_SECURITY_DISABLED, &security_flags); |
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return security_flags; |
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} |
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static int intel_security_freeze(struct nvdimm *nvdimm) |
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{ |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_freeze_lock cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_command = NVDIMM_INTEL_FREEZE_LOCK, |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_out = ND_INTEL_STATUS_SIZE, |
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.nd_fw_size = ND_INTEL_STATUS_SIZE, |
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}, |
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}; |
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int rc; |
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if (!test_bit(NVDIMM_INTEL_FREEZE_LOCK, &nfit_mem->dsm_mask)) |
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return -ENOTTY; |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0) |
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return rc; |
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if (nd_cmd.cmd.status) |
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return -EIO; |
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return 0; |
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} |
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static int intel_security_change_key(struct nvdimm *nvdimm, |
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const struct nvdimm_key_data *old_data, |
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const struct nvdimm_key_data *new_data, |
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enum nvdimm_passphrase_type ptype) |
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{ |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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unsigned int cmd = ptype == NVDIMM_MASTER ? |
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NVDIMM_INTEL_SET_MASTER_PASSPHRASE : |
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NVDIMM_INTEL_SET_PASSPHRASE; |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_set_passphrase cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE * 2, |
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.nd_size_out = ND_INTEL_STATUS_SIZE, |
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.nd_fw_size = ND_INTEL_STATUS_SIZE, |
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.nd_command = cmd, |
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}, |
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}; |
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int rc; |
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if (!test_bit(cmd, &nfit_mem->dsm_mask)) |
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return -ENOTTY; |
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memcpy(nd_cmd.cmd.old_pass, old_data->data, |
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sizeof(nd_cmd.cmd.old_pass)); |
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memcpy(nd_cmd.cmd.new_pass, new_data->data, |
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sizeof(nd_cmd.cmd.new_pass)); |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0) |
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return rc; |
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switch (nd_cmd.cmd.status) { |
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case 0: |
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return 0; |
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case ND_INTEL_STATUS_INVALID_PASS: |
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return -EINVAL; |
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case ND_INTEL_STATUS_NOT_SUPPORTED: |
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return -EOPNOTSUPP; |
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case ND_INTEL_STATUS_INVALID_STATE: |
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default: |
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return -EIO; |
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} |
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} |
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static void nvdimm_invalidate_cache(void); |
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static int __maybe_unused intel_security_unlock(struct nvdimm *nvdimm, |
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const struct nvdimm_key_data *key_data) |
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{ |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_unlock_unit cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_command = NVDIMM_INTEL_UNLOCK_UNIT, |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE, |
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.nd_size_out = ND_INTEL_STATUS_SIZE, |
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.nd_fw_size = ND_INTEL_STATUS_SIZE, |
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}, |
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}; |
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int rc; |
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if (!test_bit(NVDIMM_INTEL_UNLOCK_UNIT, &nfit_mem->dsm_mask)) |
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return -ENOTTY; |
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memcpy(nd_cmd.cmd.passphrase, key_data->data, |
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sizeof(nd_cmd.cmd.passphrase)); |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0) |
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return rc; |
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switch (nd_cmd.cmd.status) { |
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case 0: |
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break; |
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case ND_INTEL_STATUS_INVALID_PASS: |
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return -EINVAL; |
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default: |
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return -EIO; |
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} |
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/* DIMM unlocked, invalidate all CPU caches before we read it */ |
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nvdimm_invalidate_cache(); |
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return 0; |
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} |
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static int intel_security_disable(struct nvdimm *nvdimm, |
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const struct nvdimm_key_data *key_data) |
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{ |
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int rc; |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_disable_passphrase cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_command = NVDIMM_INTEL_DISABLE_PASSPHRASE, |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE, |
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.nd_size_out = ND_INTEL_STATUS_SIZE, |
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.nd_fw_size = ND_INTEL_STATUS_SIZE, |
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}, |
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}; |
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if (!test_bit(NVDIMM_INTEL_DISABLE_PASSPHRASE, &nfit_mem->dsm_mask)) |
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return -ENOTTY; |
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memcpy(nd_cmd.cmd.passphrase, key_data->data, |
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sizeof(nd_cmd.cmd.passphrase)); |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0) |
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return rc; |
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switch (nd_cmd.cmd.status) { |
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case 0: |
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break; |
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case ND_INTEL_STATUS_INVALID_PASS: |
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return -EINVAL; |
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case ND_INTEL_STATUS_INVALID_STATE: |
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default: |
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return -ENXIO; |
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} |
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return 0; |
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} |
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static int __maybe_unused intel_security_erase(struct nvdimm *nvdimm, |
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const struct nvdimm_key_data *key, |
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enum nvdimm_passphrase_type ptype) |
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{ |
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int rc; |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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unsigned int cmd = ptype == NVDIMM_MASTER ? |
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NVDIMM_INTEL_MASTER_SECURE_ERASE : NVDIMM_INTEL_SECURE_ERASE; |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_secure_erase cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE, |
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.nd_size_out = ND_INTEL_STATUS_SIZE, |
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.nd_fw_size = ND_INTEL_STATUS_SIZE, |
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.nd_command = cmd, |
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}, |
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}; |
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if (!test_bit(cmd, &nfit_mem->dsm_mask)) |
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return -ENOTTY; |
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/* flush all cache before we erase DIMM */ |
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nvdimm_invalidate_cache(); |
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memcpy(nd_cmd.cmd.passphrase, key->data, |
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sizeof(nd_cmd.cmd.passphrase)); |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0) |
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return rc; |
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switch (nd_cmd.cmd.status) { |
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case 0: |
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break; |
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case ND_INTEL_STATUS_NOT_SUPPORTED: |
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return -EOPNOTSUPP; |
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case ND_INTEL_STATUS_INVALID_PASS: |
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return -EINVAL; |
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case ND_INTEL_STATUS_INVALID_STATE: |
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default: |
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return -ENXIO; |
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} |
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/* DIMM erased, invalidate all CPU caches before we read it */ |
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nvdimm_invalidate_cache(); |
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return 0; |
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} |
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static int __maybe_unused intel_security_query_overwrite(struct nvdimm *nvdimm) |
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{ |
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int rc; |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_query_overwrite cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_command = NVDIMM_INTEL_QUERY_OVERWRITE, |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_out = ND_INTEL_STATUS_SIZE, |
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.nd_fw_size = ND_INTEL_STATUS_SIZE, |
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}, |
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}; |
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if (!test_bit(NVDIMM_INTEL_QUERY_OVERWRITE, &nfit_mem->dsm_mask)) |
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return -ENOTTY; |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0) |
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return rc; |
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switch (nd_cmd.cmd.status) { |
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case 0: |
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break; |
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case ND_INTEL_STATUS_OQUERY_INPROGRESS: |
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return -EBUSY; |
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default: |
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return -ENXIO; |
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} |
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/* flush all cache before we make the nvdimms available */ |
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nvdimm_invalidate_cache(); |
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return 0; |
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} |
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static int __maybe_unused intel_security_overwrite(struct nvdimm *nvdimm, |
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const struct nvdimm_key_data *nkey) |
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{ |
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int rc; |
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_overwrite cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_command = NVDIMM_INTEL_OVERWRITE, |
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.nd_family = NVDIMM_FAMILY_INTEL, |
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE, |
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.nd_size_out = ND_INTEL_STATUS_SIZE, |
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.nd_fw_size = ND_INTEL_STATUS_SIZE, |
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}, |
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}; |
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if (!test_bit(NVDIMM_INTEL_OVERWRITE, &nfit_mem->dsm_mask)) |
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return -ENOTTY; |
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/* flush all cache before we erase DIMM */ |
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nvdimm_invalidate_cache(); |
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memcpy(nd_cmd.cmd.passphrase, nkey->data, |
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sizeof(nd_cmd.cmd.passphrase)); |
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
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if (rc < 0) |
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return rc; |
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switch (nd_cmd.cmd.status) { |
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case 0: |
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return 0; |
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case ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED: |
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return -ENOTSUPP; |
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case ND_INTEL_STATUS_INVALID_PASS: |
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return -EINVAL; |
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case ND_INTEL_STATUS_INVALID_STATE: |
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default: |
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return -ENXIO; |
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} |
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} |
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/* |
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* TODO: define a cross arch wbinvd equivalent when/if |
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* NVDIMM_FAMILY_INTEL command support arrives on another arch. |
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*/ |
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#ifdef CONFIG_X86 |
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static void nvdimm_invalidate_cache(void) |
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{ |
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wbinvd_on_all_cpus(); |
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} |
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#else |
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static void nvdimm_invalidate_cache(void) |
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{ |
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WARN_ON_ONCE("cache invalidation required after unlock\n"); |
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} |
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#endif |
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static const struct nvdimm_security_ops __intel_security_ops = { |
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.get_flags = intel_security_flags, |
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.freeze = intel_security_freeze, |
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.change_key = intel_security_change_key, |
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.disable = intel_security_disable, |
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#ifdef CONFIG_X86 |
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.unlock = intel_security_unlock, |
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.erase = intel_security_erase, |
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.overwrite = intel_security_overwrite, |
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.query_overwrite = intel_security_query_overwrite, |
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#endif |
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}; |
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const struct nvdimm_security_ops *intel_security_ops = &__intel_security_ops; |
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static int intel_bus_fwa_businfo(struct nvdimm_bus_descriptor *nd_desc, |
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struct nd_intel_bus_fw_activate_businfo *info) |
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{ |
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struct { |
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struct nd_cmd_pkg pkg; |
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struct nd_intel_bus_fw_activate_businfo cmd; |
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} nd_cmd = { |
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.pkg = { |
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.nd_command = NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO, |
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.nd_family = NVDIMM_BUS_FAMILY_INTEL, |
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.nd_size_out = |
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sizeof(struct nd_intel_bus_fw_activate_businfo), |
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.nd_fw_size = |
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sizeof(struct nd_intel_bus_fw_activate_businfo), |
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}, |
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}; |
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int rc; |
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rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), |
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NULL); |
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*info = nd_cmd.cmd; |
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return rc; |
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} |
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/* The fw_ops expect to be called with the nvdimm_bus_lock() held */ |
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static enum nvdimm_fwa_state intel_bus_fwa_state( |
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struct nvdimm_bus_descriptor *nd_desc) |
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{ |
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struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
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struct nd_intel_bus_fw_activate_businfo info; |
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struct device *dev = acpi_desc->dev; |
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enum nvdimm_fwa_state state; |
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int rc; |
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|
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/* |
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* It should not be possible for platform firmware to return |
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* busy because activate is a synchronous operation. Treat it |
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* similar to invalid, i.e. always refresh / poll the status. |
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*/ |
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switch (acpi_desc->fwa_state) { |
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case NVDIMM_FWA_INVALID: |
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case NVDIMM_FWA_BUSY: |
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break; |
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default: |
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/* check if capability needs to be refreshed */ |
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if (acpi_desc->fwa_cap == NVDIMM_FWA_CAP_INVALID) |
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break; |
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return acpi_desc->fwa_state; |
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} |
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/* Refresh with platform firmware */ |
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rc = intel_bus_fwa_businfo(nd_desc, &info); |
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if (rc) |
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return NVDIMM_FWA_INVALID; |
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switch (info.state) { |
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case ND_INTEL_FWA_IDLE: |
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state = NVDIMM_FWA_IDLE; |
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break; |
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case ND_INTEL_FWA_BUSY: |
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state = NVDIMM_FWA_BUSY; |
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break; |
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case ND_INTEL_FWA_ARMED: |
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if (info.activate_tmo > info.max_quiesce_tmo) |
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state = NVDIMM_FWA_ARM_OVERFLOW; |
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else |
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state = NVDIMM_FWA_ARMED; |
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break; |
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default: |
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dev_err_once(dev, "invalid firmware activate state %d\n", |
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info.state); |
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return NVDIMM_FWA_INVALID; |
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} |
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/* |
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* Capability data is available in the same payload as state. It |
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* is expected to be static. |
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*/ |
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if (acpi_desc->fwa_cap == NVDIMM_FWA_CAP_INVALID) { |
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if (info.capability & ND_INTEL_BUS_FWA_CAP_FWQUIESCE) |
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acpi_desc->fwa_cap = NVDIMM_FWA_CAP_QUIESCE; |
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else if (info.capability & ND_INTEL_BUS_FWA_CAP_OSQUIESCE) { |
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/* |
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* Skip hibernate cycle by default if platform |
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* indicates that it does not need devices to be |
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* quiesced. |
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*/ |
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acpi_desc->fwa_cap = NVDIMM_FWA_CAP_LIVE; |
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} else |
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acpi_desc->fwa_cap = NVDIMM_FWA_CAP_NONE; |
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} |
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|
acpi_desc->fwa_state = state; |
|
|
|
return state; |
|
} |
|
|
|
static enum nvdimm_fwa_capability intel_bus_fwa_capability( |
|
struct nvdimm_bus_descriptor *nd_desc) |
|
{ |
|
struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
|
|
|
if (acpi_desc->fwa_cap > NVDIMM_FWA_CAP_INVALID) |
|
return acpi_desc->fwa_cap; |
|
|
|
if (intel_bus_fwa_state(nd_desc) > NVDIMM_FWA_INVALID) |
|
return acpi_desc->fwa_cap; |
|
|
|
return NVDIMM_FWA_CAP_INVALID; |
|
} |
|
|
|
static int intel_bus_fwa_activate(struct nvdimm_bus_descriptor *nd_desc) |
|
{ |
|
struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
|
struct { |
|
struct nd_cmd_pkg pkg; |
|
struct nd_intel_bus_fw_activate cmd; |
|
} nd_cmd = { |
|
.pkg = { |
|
.nd_command = NVDIMM_BUS_INTEL_FW_ACTIVATE, |
|
.nd_family = NVDIMM_BUS_FAMILY_INTEL, |
|
.nd_size_in = sizeof(nd_cmd.cmd.iodev_state), |
|
.nd_size_out = |
|
sizeof(struct nd_intel_bus_fw_activate), |
|
.nd_fw_size = |
|
sizeof(struct nd_intel_bus_fw_activate), |
|
}, |
|
/* |
|
* Even though activate is run from a suspended context, |
|
* for safety, still ask platform firmware to force |
|
* quiesce devices by default. Let a module |
|
* parameter override that policy. |
|
*/ |
|
.cmd = { |
|
.iodev_state = acpi_desc->fwa_noidle |
|
? ND_INTEL_BUS_FWA_IODEV_OS_IDLE |
|
: ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE, |
|
}, |
|
}; |
|
int rc; |
|
|
|
switch (intel_bus_fwa_state(nd_desc)) { |
|
case NVDIMM_FWA_ARMED: |
|
case NVDIMM_FWA_ARM_OVERFLOW: |
|
break; |
|
default: |
|
return -ENXIO; |
|
} |
|
|
|
rc = nd_desc->ndctl(nd_desc, NULL, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), |
|
NULL); |
|
|
|
/* |
|
* Whether the command succeeded, or failed, the agent checking |
|
* for the result needs to query the DIMMs individually. |
|
* Increment the activation count to invalidate all the DIMM |
|
* states at once (it's otherwise not possible to take |
|
* acpi_desc->init_mutex in this context) |
|
*/ |
|
acpi_desc->fwa_state = NVDIMM_FWA_INVALID; |
|
acpi_desc->fwa_count++; |
|
|
|
dev_dbg(acpi_desc->dev, "result: %d\n", rc); |
|
|
|
return rc; |
|
} |
|
|
|
static const struct nvdimm_bus_fw_ops __intel_bus_fw_ops = { |
|
.activate_state = intel_bus_fwa_state, |
|
.capability = intel_bus_fwa_capability, |
|
.activate = intel_bus_fwa_activate, |
|
}; |
|
|
|
const struct nvdimm_bus_fw_ops *intel_bus_fw_ops = &__intel_bus_fw_ops; |
|
|
|
static int intel_fwa_dimminfo(struct nvdimm *nvdimm, |
|
struct nd_intel_fw_activate_dimminfo *info) |
|
{ |
|
struct { |
|
struct nd_cmd_pkg pkg; |
|
struct nd_intel_fw_activate_dimminfo cmd; |
|
} nd_cmd = { |
|
.pkg = { |
|
.nd_command = NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO, |
|
.nd_family = NVDIMM_FAMILY_INTEL, |
|
.nd_size_out = |
|
sizeof(struct nd_intel_fw_activate_dimminfo), |
|
.nd_fw_size = |
|
sizeof(struct nd_intel_fw_activate_dimminfo), |
|
}, |
|
}; |
|
int rc; |
|
|
|
rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
|
*info = nd_cmd.cmd; |
|
return rc; |
|
} |
|
|
|
static enum nvdimm_fwa_state intel_fwa_state(struct nvdimm *nvdimm) |
|
{ |
|
struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
|
struct acpi_nfit_desc *acpi_desc = nfit_mem->acpi_desc; |
|
struct nd_intel_fw_activate_dimminfo info; |
|
int rc; |
|
|
|
/* |
|
* Similar to the bus state, since activate is synchronous the |
|
* busy state should resolve within the context of 'activate'. |
|
*/ |
|
switch (nfit_mem->fwa_state) { |
|
case NVDIMM_FWA_INVALID: |
|
case NVDIMM_FWA_BUSY: |
|
break; |
|
default: |
|
/* If no activations occurred the old state is still valid */ |
|
if (nfit_mem->fwa_count == acpi_desc->fwa_count) |
|
return nfit_mem->fwa_state; |
|
} |
|
|
|
rc = intel_fwa_dimminfo(nvdimm, &info); |
|
if (rc) |
|
return NVDIMM_FWA_INVALID; |
|
|
|
switch (info.state) { |
|
case ND_INTEL_FWA_IDLE: |
|
nfit_mem->fwa_state = NVDIMM_FWA_IDLE; |
|
break; |
|
case ND_INTEL_FWA_BUSY: |
|
nfit_mem->fwa_state = NVDIMM_FWA_BUSY; |
|
break; |
|
case ND_INTEL_FWA_ARMED: |
|
nfit_mem->fwa_state = NVDIMM_FWA_ARMED; |
|
break; |
|
default: |
|
nfit_mem->fwa_state = NVDIMM_FWA_INVALID; |
|
break; |
|
} |
|
|
|
switch (info.result) { |
|
case ND_INTEL_DIMM_FWA_NONE: |
|
nfit_mem->fwa_result = NVDIMM_FWA_RESULT_NONE; |
|
break; |
|
case ND_INTEL_DIMM_FWA_SUCCESS: |
|
nfit_mem->fwa_result = NVDIMM_FWA_RESULT_SUCCESS; |
|
break; |
|
case ND_INTEL_DIMM_FWA_NOTSTAGED: |
|
nfit_mem->fwa_result = NVDIMM_FWA_RESULT_NOTSTAGED; |
|
break; |
|
case ND_INTEL_DIMM_FWA_NEEDRESET: |
|
nfit_mem->fwa_result = NVDIMM_FWA_RESULT_NEEDRESET; |
|
break; |
|
case ND_INTEL_DIMM_FWA_MEDIAFAILED: |
|
case ND_INTEL_DIMM_FWA_ABORT: |
|
case ND_INTEL_DIMM_FWA_NOTSUPP: |
|
case ND_INTEL_DIMM_FWA_ERROR: |
|
default: |
|
nfit_mem->fwa_result = NVDIMM_FWA_RESULT_FAIL; |
|
break; |
|
} |
|
|
|
nfit_mem->fwa_count = acpi_desc->fwa_count; |
|
|
|
return nfit_mem->fwa_state; |
|
} |
|
|
|
static enum nvdimm_fwa_result intel_fwa_result(struct nvdimm *nvdimm) |
|
{ |
|
struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
|
struct acpi_nfit_desc *acpi_desc = nfit_mem->acpi_desc; |
|
|
|
if (nfit_mem->fwa_count == acpi_desc->fwa_count |
|
&& nfit_mem->fwa_result > NVDIMM_FWA_RESULT_INVALID) |
|
return nfit_mem->fwa_result; |
|
|
|
if (intel_fwa_state(nvdimm) > NVDIMM_FWA_INVALID) |
|
return nfit_mem->fwa_result; |
|
|
|
return NVDIMM_FWA_RESULT_INVALID; |
|
} |
|
|
|
static int intel_fwa_arm(struct nvdimm *nvdimm, enum nvdimm_fwa_trigger arm) |
|
{ |
|
struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm); |
|
struct acpi_nfit_desc *acpi_desc = nfit_mem->acpi_desc; |
|
struct { |
|
struct nd_cmd_pkg pkg; |
|
struct nd_intel_fw_activate_arm cmd; |
|
} nd_cmd = { |
|
.pkg = { |
|
.nd_command = NVDIMM_INTEL_FW_ACTIVATE_ARM, |
|
.nd_family = NVDIMM_FAMILY_INTEL, |
|
.nd_size_in = sizeof(nd_cmd.cmd.activate_arm), |
|
.nd_size_out = |
|
sizeof(struct nd_intel_fw_activate_arm), |
|
.nd_fw_size = |
|
sizeof(struct nd_intel_fw_activate_arm), |
|
}, |
|
.cmd = { |
|
.activate_arm = arm == NVDIMM_FWA_ARM |
|
? ND_INTEL_DIMM_FWA_ARM |
|
: ND_INTEL_DIMM_FWA_DISARM, |
|
}, |
|
}; |
|
int rc; |
|
|
|
switch (intel_fwa_state(nvdimm)) { |
|
case NVDIMM_FWA_INVALID: |
|
return -ENXIO; |
|
case NVDIMM_FWA_BUSY: |
|
return -EBUSY; |
|
case NVDIMM_FWA_IDLE: |
|
if (arm == NVDIMM_FWA_DISARM) |
|
return 0; |
|
break; |
|
case NVDIMM_FWA_ARMED: |
|
if (arm == NVDIMM_FWA_ARM) |
|
return 0; |
|
break; |
|
default: |
|
return -ENXIO; |
|
} |
|
|
|
/* |
|
* Invalidate the bus-level state, now that we're committed to |
|
* changing the 'arm' state. |
|
*/ |
|
acpi_desc->fwa_state = NVDIMM_FWA_INVALID; |
|
nfit_mem->fwa_state = NVDIMM_FWA_INVALID; |
|
|
|
rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL); |
|
|
|
dev_dbg(acpi_desc->dev, "%s result: %d\n", arm == NVDIMM_FWA_ARM |
|
? "arm" : "disarm", rc); |
|
return rc; |
|
} |
|
|
|
static const struct nvdimm_fw_ops __intel_fw_ops = { |
|
.activate_state = intel_fwa_state, |
|
.activate_result = intel_fwa_result, |
|
.arm = intel_fwa_arm, |
|
}; |
|
|
|
const struct nvdimm_fw_ops *intel_fw_ops = &__intel_fw_ops;
|
|
|