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38 lines
855 B
38 lines
855 B
/* SPDX-License-Identifier: GPL-2.0 |
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* |
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* SH3 CPU-specific DMA definitions, used by both DMA drivers |
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* |
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* Copyright (C) 2010 Guennadi Liakhovetski <[email protected]> |
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*/ |
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#ifndef CPU_DMA_REGISTER_H |
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#define CPU_DMA_REGISTER_H |
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#define CHCR_TS_LOW_MASK 0x18 |
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#define CHCR_TS_LOW_SHIFT 3 |
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#define CHCR_TS_HIGH_MASK 0 |
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#define CHCR_TS_HIGH_SHIFT 0 |
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#define DMAOR_INIT DMAOR_DME |
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/* |
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* The SuperH DMAC supports a number of transmit sizes, we list them here, |
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* with their respective values as they appear in the CHCR registers. |
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*/ |
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enum { |
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XMIT_SZ_8BIT, |
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XMIT_SZ_16BIT, |
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XMIT_SZ_32BIT, |
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XMIT_SZ_128BIT, |
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}; |
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/* log2(size / 8) - used to calculate number of transfers */ |
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#define TS_SHIFT { \ |
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[XMIT_SZ_8BIT] = 0, \ |
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[XMIT_SZ_16BIT] = 1, \ |
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[XMIT_SZ_32BIT] = 2, \ |
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[XMIT_SZ_128BIT] = 4, \ |
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} |
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#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT) |
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#endif
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