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861 lines
20 KiB
861 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2016,2017 IBM Corporation. |
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*/ |
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#define pr_fmt(fmt) "xive: " fmt |
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#include <linux/types.h> |
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#include <linux/irq.h> |
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#include <linux/debugfs.h> |
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#include <linux/smp.h> |
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#include <linux/interrupt.h> |
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#include <linux/seq_file.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/delay.h> |
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#include <linux/cpumask.h> |
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#include <linux/mm.h> |
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#include <linux/kmemleak.h> |
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#include <asm/machdep.h> |
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#include <asm/prom.h> |
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#include <asm/io.h> |
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#include <asm/smp.h> |
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#include <asm/irq.h> |
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#include <asm/errno.h> |
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#include <asm/xive.h> |
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#include <asm/xive-regs.h> |
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#include <asm/opal.h> |
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#include <asm/kvm_ppc.h> |
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#include "xive-internal.h" |
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static u32 xive_provision_size; |
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static u32 *xive_provision_chips; |
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static u32 xive_provision_chip_count; |
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static u32 xive_queue_shift; |
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static u32 xive_pool_vps = XIVE_INVALID_VP; |
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static struct kmem_cache *xive_provision_cache; |
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static bool xive_has_single_esc; |
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static bool xive_has_save_restore; |
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int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) |
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{ |
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__be64 flags, eoi_page, trig_page; |
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__be32 esb_shift, src_chip; |
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u64 opal_flags; |
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s64 rc; |
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memset(data, 0, sizeof(*data)); |
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rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page, |
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&esb_shift, &src_chip); |
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if (rc) { |
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pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n", |
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hw_irq, rc); |
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return -EINVAL; |
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} |
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opal_flags = be64_to_cpu(flags); |
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if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI) |
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data->flags |= XIVE_IRQ_FLAG_STORE_EOI; |
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if (opal_flags & OPAL_XIVE_IRQ_LSI) |
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data->flags |= XIVE_IRQ_FLAG_LSI; |
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data->eoi_page = be64_to_cpu(eoi_page); |
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data->trig_page = be64_to_cpu(trig_page); |
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data->esb_shift = be32_to_cpu(esb_shift); |
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data->src_chip = be32_to_cpu(src_chip); |
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data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift); |
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if (!data->eoi_mmio) { |
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pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq); |
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return -ENOMEM; |
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} |
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data->hw_irq = hw_irq; |
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if (!data->trig_page) |
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return 0; |
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if (data->trig_page == data->eoi_page) { |
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data->trig_mmio = data->eoi_mmio; |
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return 0; |
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} |
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data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift); |
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if (!data->trig_mmio) { |
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pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq); |
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return -ENOMEM; |
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} |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(xive_native_populate_irq_data); |
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int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) |
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{ |
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s64 rc; |
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for (;;) { |
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rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); |
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if (rc != OPAL_BUSY) |
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break; |
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msleep(OPAL_BUSY_DELAY_MS); |
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} |
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return rc == 0 ? 0 : -ENXIO; |
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} |
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EXPORT_SYMBOL_GPL(xive_native_configure_irq); |
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static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, |
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u32 *sw_irq) |
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{ |
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s64 rc; |
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__be64 vp; |
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__be32 lirq; |
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rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq); |
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*target = be64_to_cpu(vp); |
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*sw_irq = be32_to_cpu(lirq); |
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return rc == 0 ? 0 : -ENXIO; |
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} |
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#define vp_err(vp, fmt, ...) pr_err("VP[0x%x]: " fmt, vp, ##__VA_ARGS__) |
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/* This can be called multiple time to change a queue configuration */ |
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int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, |
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__be32 *qpage, u32 order, bool can_escalate) |
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{ |
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s64 rc = 0; |
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__be64 qeoi_page_be; |
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__be32 esc_irq_be; |
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u64 flags, qpage_phys; |
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/* If there's an actual queue page, clean it */ |
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if (order) { |
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if (WARN_ON(!qpage)) |
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return -EINVAL; |
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qpage_phys = __pa(qpage); |
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} else |
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qpage_phys = 0; |
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/* Initialize the rest of the fields */ |
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q->msk = order ? ((1u << (order - 2)) - 1) : 0; |
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q->idx = 0; |
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q->toggle = 0; |
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rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, |
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&qeoi_page_be, |
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&esc_irq_be, |
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NULL); |
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if (rc) { |
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vp_err(vp_id, "Failed to get queue %d info : %lld\n", prio, rc); |
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rc = -EIO; |
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goto fail; |
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} |
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q->eoi_phys = be64_to_cpu(qeoi_page_be); |
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/* Default flags */ |
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flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED; |
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/* Escalation needed ? */ |
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if (can_escalate) { |
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q->esc_irq = be32_to_cpu(esc_irq_be); |
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flags |= OPAL_XIVE_EQ_ESCALATE; |
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} |
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/* Configure and enable the queue in HW */ |
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for (;;) { |
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rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); |
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if (rc != OPAL_BUSY) |
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break; |
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msleep(OPAL_BUSY_DELAY_MS); |
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} |
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if (rc) { |
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vp_err(vp_id, "Failed to set queue %d info: %lld\n", prio, rc); |
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rc = -EIO; |
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} else { |
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/* |
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* KVM code requires all of the above to be visible before |
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* q->qpage is set due to how it manages IPI EOIs |
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*/ |
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wmb(); |
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q->qpage = qpage; |
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} |
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fail: |
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return rc; |
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} |
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EXPORT_SYMBOL_GPL(xive_native_configure_queue); |
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static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) |
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{ |
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s64 rc; |
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/* Disable the queue in HW */ |
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for (;;) { |
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rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0); |
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if (rc != OPAL_BUSY) |
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break; |
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msleep(OPAL_BUSY_DELAY_MS); |
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} |
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if (rc) |
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vp_err(vp_id, "Failed to disable queue %d : %lld\n", prio, rc); |
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} |
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void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) |
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{ |
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__xive_native_disable_queue(vp_id, q, prio); |
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} |
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EXPORT_SYMBOL_GPL(xive_native_disable_queue); |
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static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) |
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{ |
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struct xive_q *q = &xc->queue[prio]; |
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__be32 *qpage; |
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qpage = xive_queue_page_alloc(cpu, xive_queue_shift); |
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if (IS_ERR(qpage)) |
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return PTR_ERR(qpage); |
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return xive_native_configure_queue(get_hard_smp_processor_id(cpu), |
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q, prio, qpage, xive_queue_shift, false); |
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} |
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static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) |
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{ |
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struct xive_q *q = &xc->queue[prio]; |
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unsigned int alloc_order; |
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/* |
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* We use the variant with no iounmap as this is called on exec |
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* from an IPI and iounmap isn't safe |
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*/ |
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__xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio); |
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alloc_order = xive_alloc_order(xive_queue_shift); |
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free_pages((unsigned long)q->qpage, alloc_order); |
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q->qpage = NULL; |
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} |
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static bool xive_native_match(struct device_node *node) |
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{ |
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return of_device_is_compatible(node, "ibm,opal-xive-vc"); |
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} |
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static s64 opal_xive_allocate_irq(u32 chip_id) |
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{ |
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s64 irq = opal_xive_allocate_irq_raw(chip_id); |
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/* |
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* Old versions of skiboot can incorrectly return 0xffffffff to |
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* indicate no space, fix it up here. |
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*/ |
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return irq == 0xffffffff ? OPAL_RESOURCE : irq; |
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} |
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#ifdef CONFIG_SMP |
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static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) |
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{ |
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s64 irq; |
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/* Allocate an IPI and populate info about it */ |
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for (;;) { |
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irq = opal_xive_allocate_irq(xc->chip_id); |
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if (irq == OPAL_BUSY) { |
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msleep(OPAL_BUSY_DELAY_MS); |
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continue; |
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} |
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if (irq < 0) { |
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pr_err("Failed to allocate IPI on CPU %d\n", cpu); |
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return -ENXIO; |
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} |
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xc->hw_ipi = irq; |
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break; |
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} |
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return 0; |
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} |
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#endif /* CONFIG_SMP */ |
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u32 xive_native_alloc_irq_on_chip(u32 chip_id) |
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{ |
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s64 rc; |
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for (;;) { |
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rc = opal_xive_allocate_irq(chip_id); |
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if (rc != OPAL_BUSY) |
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break; |
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msleep(OPAL_BUSY_DELAY_MS); |
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} |
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if (rc < 0) |
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return 0; |
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return rc; |
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} |
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EXPORT_SYMBOL_GPL(xive_native_alloc_irq_on_chip); |
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void xive_native_free_irq(u32 irq) |
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{ |
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for (;;) { |
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s64 rc = opal_xive_free_irq(irq); |
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if (rc != OPAL_BUSY) |
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break; |
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msleep(OPAL_BUSY_DELAY_MS); |
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} |
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} |
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EXPORT_SYMBOL_GPL(xive_native_free_irq); |
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#ifdef CONFIG_SMP |
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static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) |
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{ |
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s64 rc; |
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/* Free the IPI */ |
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if (xc->hw_ipi == XIVE_BAD_IRQ) |
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return; |
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for (;;) { |
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rc = opal_xive_free_irq(xc->hw_ipi); |
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if (rc == OPAL_BUSY) { |
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msleep(OPAL_BUSY_DELAY_MS); |
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continue; |
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} |
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xc->hw_ipi = XIVE_BAD_IRQ; |
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break; |
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} |
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} |
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#endif /* CONFIG_SMP */ |
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static void xive_native_shutdown(void) |
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{ |
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/* Switch the XIVE to emulation mode */ |
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opal_xive_reset(OPAL_XIVE_MODE_EMU); |
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} |
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/* |
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* Perform an "ack" cycle on the current thread, thus |
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* grabbing the pending active priorities and updating |
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* the CPPR to the most favored one. |
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*/ |
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static void xive_native_update_pending(struct xive_cpu *xc) |
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{ |
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u8 he, cppr; |
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u16 ack; |
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/* Perform the acknowledge hypervisor to register cycle */ |
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ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG)); |
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/* Synchronize subsequent queue accesses */ |
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mb(); |
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/* |
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* Grab the CPPR and the "HE" field which indicates the source |
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* of the hypervisor interrupt (if any) |
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*/ |
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cppr = ack & 0xff; |
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he = (ack >> 8) >> 6; |
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switch(he) { |
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case TM_QW3_NSR_HE_NONE: /* Nothing to see here */ |
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break; |
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case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */ |
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if (cppr == 0xff) |
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return; |
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/* Mark the priority pending */ |
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xc->pending_prio |= 1 << cppr; |
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/* |
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* A new interrupt should never have a CPPR less favored |
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* than our current one. |
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*/ |
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if (cppr >= xc->cppr) |
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pr_err("CPU %d odd ack CPPR, got %d at %d\n", |
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smp_processor_id(), cppr, xc->cppr); |
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/* Update our idea of what the CPPR is */ |
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xc->cppr = cppr; |
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break; |
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case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */ |
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case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */ |
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pr_err("CPU %d got unexpected interrupt type HE=%d\n", |
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smp_processor_id(), he); |
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return; |
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} |
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} |
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static void xive_native_prepare_cpu(unsigned int cpu, struct xive_cpu *xc) |
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{ |
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xc->chip_id = cpu_to_chip_id(cpu); |
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} |
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static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) |
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{ |
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s64 rc; |
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u32 vp; |
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__be64 vp_cam_be; |
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u64 vp_cam; |
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if (xive_pool_vps == XIVE_INVALID_VP) |
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return; |
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/* Check if pool VP already active, if it is, pull it */ |
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if (in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2) & TM_QW2W2_VP) |
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in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); |
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/* Enable the pool VP */ |
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vp = xive_pool_vps + cpu; |
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for (;;) { |
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rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0); |
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if (rc != OPAL_BUSY) |
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break; |
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msleep(OPAL_BUSY_DELAY_MS); |
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} |
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if (rc) { |
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pr_err("Failed to enable pool VP on CPU %d\n", cpu); |
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return; |
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} |
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/* Grab it's CAM value */ |
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rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL); |
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if (rc) { |
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pr_err("Failed to get pool VP info CPU %d\n", cpu); |
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return; |
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} |
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vp_cam = be64_to_cpu(vp_cam_be); |
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/* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */ |
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out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff); |
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out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | vp_cam); |
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} |
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static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) |
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{ |
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s64 rc; |
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u32 vp; |
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if (xive_pool_vps == XIVE_INVALID_VP) |
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return; |
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/* Pull the pool VP from the CPU */ |
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in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); |
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/* Disable it */ |
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vp = xive_pool_vps + cpu; |
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for (;;) { |
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rc = opal_xive_set_vp_info(vp, 0, 0); |
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if (rc != OPAL_BUSY) |
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break; |
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msleep(OPAL_BUSY_DELAY_MS); |
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} |
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} |
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void xive_native_sync_source(u32 hw_irq) |
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{ |
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opal_xive_sync(XIVE_SYNC_EAS, hw_irq); |
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} |
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EXPORT_SYMBOL_GPL(xive_native_sync_source); |
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void xive_native_sync_queue(u32 hw_irq) |
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{ |
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opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq); |
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} |
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EXPORT_SYMBOL_GPL(xive_native_sync_queue); |
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static const struct xive_ops xive_native_ops = { |
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.populate_irq_data = xive_native_populate_irq_data, |
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.configure_irq = xive_native_configure_irq, |
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.get_irq_config = xive_native_get_irq_config, |
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.setup_queue = xive_native_setup_queue, |
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.cleanup_queue = xive_native_cleanup_queue, |
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.match = xive_native_match, |
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.shutdown = xive_native_shutdown, |
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.update_pending = xive_native_update_pending, |
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.prepare_cpu = xive_native_prepare_cpu, |
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.setup_cpu = xive_native_setup_cpu, |
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.teardown_cpu = xive_native_teardown_cpu, |
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.sync_source = xive_native_sync_source, |
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#ifdef CONFIG_SMP |
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.get_ipi = xive_native_get_ipi, |
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.put_ipi = xive_native_put_ipi, |
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#endif /* CONFIG_SMP */ |
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.name = "native", |
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}; |
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static bool xive_parse_provisioning(struct device_node *np) |
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{ |
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int rc; |
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if (of_property_read_u32(np, "ibm,xive-provision-page-size", |
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&xive_provision_size) < 0) |
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return true; |
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rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4); |
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if (rc < 0) { |
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pr_err("Error %d getting provision chips array\n", rc); |
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return false; |
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} |
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xive_provision_chip_count = rc; |
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if (rc == 0) |
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return true; |
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xive_provision_chips = kcalloc(4, xive_provision_chip_count, |
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GFP_KERNEL); |
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if (WARN_ON(!xive_provision_chips)) |
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return false; |
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rc = of_property_read_u32_array(np, "ibm,xive-provision-chips", |
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xive_provision_chips, |
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xive_provision_chip_count); |
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if (rc < 0) { |
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pr_err("Error %d reading provision chips array\n", rc); |
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return false; |
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} |
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xive_provision_cache = kmem_cache_create("xive-provision", |
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xive_provision_size, |
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xive_provision_size, |
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0, NULL); |
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if (!xive_provision_cache) { |
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pr_err("Failed to allocate provision cache\n"); |
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return false; |
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} |
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return true; |
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} |
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static void xive_native_setup_pools(void) |
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{ |
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/* Allocate a pool big enough */ |
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pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids); |
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xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids); |
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if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP)) |
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pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n"); |
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pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n", |
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xive_pool_vps, nr_cpu_ids); |
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} |
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u32 xive_native_default_eq_shift(void) |
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{ |
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return xive_queue_shift; |
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} |
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EXPORT_SYMBOL_GPL(xive_native_default_eq_shift); |
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|
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unsigned long xive_tima_os; |
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EXPORT_SYMBOL_GPL(xive_tima_os); |
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bool __init xive_native_init(void) |
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{ |
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struct device_node *np; |
|
struct resource r; |
|
void __iomem *tima; |
|
struct property *prop; |
|
u8 max_prio = 7; |
|
const __be32 *p; |
|
u32 val, cpu; |
|
s64 rc; |
|
|
|
if (xive_cmdline_disabled) |
|
return false; |
|
|
|
pr_devel("xive_native_init()\n"); |
|
np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe"); |
|
if (!np) { |
|
pr_devel("not found !\n"); |
|
return false; |
|
} |
|
pr_devel("Found %pOF\n", np); |
|
|
|
/* Resource 1 is HV window */ |
|
if (of_address_to_resource(np, 1, &r)) { |
|
pr_err("Failed to get thread mgmnt area resource\n"); |
|
return false; |
|
} |
|
tima = ioremap(r.start, resource_size(&r)); |
|
if (!tima) { |
|
pr_err("Failed to map thread mgmnt area\n"); |
|
return false; |
|
} |
|
|
|
/* Read number of priorities */ |
|
if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0) |
|
max_prio = val - 1; |
|
|
|
/* Iterate the EQ sizes and pick one */ |
|
of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) { |
|
xive_queue_shift = val; |
|
if (val == PAGE_SHIFT) |
|
break; |
|
} |
|
|
|
/* Do we support single escalation */ |
|
if (of_get_property(np, "single-escalation-support", NULL) != NULL) |
|
xive_has_single_esc = true; |
|
|
|
if (of_get_property(np, "vp-save-restore", NULL)) |
|
xive_has_save_restore = true; |
|
|
|
/* Configure Thread Management areas for KVM */ |
|
for_each_possible_cpu(cpu) |
|
kvmppc_set_xive_tima(cpu, r.start, tima); |
|
|
|
/* Resource 2 is OS window */ |
|
if (of_address_to_resource(np, 2, &r)) { |
|
pr_err("Failed to get thread mgmnt area resource\n"); |
|
return false; |
|
} |
|
|
|
xive_tima_os = r.start; |
|
|
|
/* Grab size of provisionning pages */ |
|
xive_parse_provisioning(np); |
|
|
|
/* Switch the XIVE to exploitation mode */ |
|
rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL); |
|
if (rc) { |
|
pr_err("Switch to exploitation mode failed with error %lld\n", rc); |
|
return false; |
|
} |
|
|
|
/* Setup some dummy HV pool VPs */ |
|
xive_native_setup_pools(); |
|
|
|
/* Initialize XIVE core with our backend */ |
|
if (!xive_core_init(np, &xive_native_ops, tima, TM_QW3_HV_PHYS, |
|
max_prio)) { |
|
opal_xive_reset(OPAL_XIVE_MODE_EMU); |
|
return false; |
|
} |
|
pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10)); |
|
return true; |
|
} |
|
|
|
static bool xive_native_provision_pages(void) |
|
{ |
|
u32 i; |
|
void *p; |
|
|
|
for (i = 0; i < xive_provision_chip_count; i++) { |
|
u32 chip = xive_provision_chips[i]; |
|
|
|
/* |
|
* XXX TODO: Try to make the allocation local to the node where |
|
* the chip resides. |
|
*/ |
|
p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL); |
|
if (!p) { |
|
pr_err("Failed to allocate provisioning page\n"); |
|
return false; |
|
} |
|
kmemleak_ignore(p); |
|
opal_xive_donate_page(chip, __pa(p)); |
|
} |
|
return true; |
|
} |
|
|
|
u32 xive_native_alloc_vp_block(u32 max_vcpus) |
|
{ |
|
s64 rc; |
|
u32 order; |
|
|
|
order = fls(max_vcpus) - 1; |
|
if (max_vcpus > (1 << order)) |
|
order++; |
|
|
|
pr_debug("VP block alloc, for max VCPUs %d use order %d\n", |
|
max_vcpus, order); |
|
|
|
for (;;) { |
|
rc = opal_xive_alloc_vp_block(order); |
|
switch (rc) { |
|
case OPAL_BUSY: |
|
msleep(OPAL_BUSY_DELAY_MS); |
|
break; |
|
case OPAL_XIVE_PROVISIONING: |
|
if (!xive_native_provision_pages()) |
|
return XIVE_INVALID_VP; |
|
break; |
|
default: |
|
if (rc < 0) { |
|
pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n", |
|
order, rc); |
|
return XIVE_INVALID_VP; |
|
} |
|
return rc; |
|
} |
|
} |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block); |
|
|
|
void xive_native_free_vp_block(u32 vp_base) |
|
{ |
|
s64 rc; |
|
|
|
if (vp_base == XIVE_INVALID_VP) |
|
return; |
|
|
|
rc = opal_xive_free_vp_block(vp_base); |
|
if (rc < 0) |
|
pr_warn("OPAL error %lld freeing VP block\n", rc); |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_free_vp_block); |
|
|
|
int xive_native_enable_vp(u32 vp_id, bool single_escalation) |
|
{ |
|
s64 rc; |
|
u64 flags = OPAL_XIVE_VP_ENABLED; |
|
|
|
if (single_escalation) |
|
flags |= OPAL_XIVE_VP_SINGLE_ESCALATION; |
|
for (;;) { |
|
rc = opal_xive_set_vp_info(vp_id, flags, 0); |
|
if (rc != OPAL_BUSY) |
|
break; |
|
msleep(OPAL_BUSY_DELAY_MS); |
|
} |
|
if (rc) |
|
vp_err(vp_id, "Failed to enable VP : %lld\n", rc); |
|
return rc ? -EIO : 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_enable_vp); |
|
|
|
int xive_native_disable_vp(u32 vp_id) |
|
{ |
|
s64 rc; |
|
|
|
for (;;) { |
|
rc = opal_xive_set_vp_info(vp_id, 0, 0); |
|
if (rc != OPAL_BUSY) |
|
break; |
|
msleep(OPAL_BUSY_DELAY_MS); |
|
} |
|
if (rc) |
|
vp_err(vp_id, "Failed to disable VP : %lld\n", rc); |
|
return rc ? -EIO : 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_disable_vp); |
|
|
|
int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id) |
|
{ |
|
__be64 vp_cam_be; |
|
__be32 vp_chip_id_be; |
|
s64 rc; |
|
|
|
rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be); |
|
if (rc) { |
|
vp_err(vp_id, "Failed to get VP info : %lld\n", rc); |
|
return -EIO; |
|
} |
|
*out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu; |
|
*out_chip_id = be32_to_cpu(vp_chip_id_be); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_get_vp_info); |
|
|
|
bool xive_native_has_single_escalation(void) |
|
{ |
|
return xive_has_single_esc; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_has_single_escalation); |
|
|
|
bool xive_native_has_save_restore(void) |
|
{ |
|
return xive_has_save_restore; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_has_save_restore); |
|
|
|
int xive_native_get_queue_info(u32 vp_id, u32 prio, |
|
u64 *out_qpage, |
|
u64 *out_qsize, |
|
u64 *out_qeoi_page, |
|
u32 *out_escalate_irq, |
|
u64 *out_qflags) |
|
{ |
|
__be64 qpage; |
|
__be64 qsize; |
|
__be64 qeoi_page; |
|
__be32 escalate_irq; |
|
__be64 qflags; |
|
s64 rc; |
|
|
|
rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize, |
|
&qeoi_page, &escalate_irq, &qflags); |
|
if (rc) { |
|
vp_err(vp_id, "failed to get queue %d info : %lld\n", prio, rc); |
|
return -EIO; |
|
} |
|
|
|
if (out_qpage) |
|
*out_qpage = be64_to_cpu(qpage); |
|
if (out_qsize) |
|
*out_qsize = be32_to_cpu(qsize); |
|
if (out_qeoi_page) |
|
*out_qeoi_page = be64_to_cpu(qeoi_page); |
|
if (out_escalate_irq) |
|
*out_escalate_irq = be32_to_cpu(escalate_irq); |
|
if (out_qflags) |
|
*out_qflags = be64_to_cpu(qflags); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_get_queue_info); |
|
|
|
int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex) |
|
{ |
|
__be32 opal_qtoggle; |
|
__be32 opal_qindex; |
|
s64 rc; |
|
|
|
rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle, |
|
&opal_qindex); |
|
if (rc) { |
|
vp_err(vp_id, "failed to get queue %d state : %lld\n", prio, rc); |
|
return -EIO; |
|
} |
|
|
|
if (qtoggle) |
|
*qtoggle = be32_to_cpu(opal_qtoggle); |
|
if (qindex) |
|
*qindex = be32_to_cpu(opal_qindex); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_get_queue_state); |
|
|
|
int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex) |
|
{ |
|
s64 rc; |
|
|
|
rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex); |
|
if (rc) { |
|
vp_err(vp_id, "failed to set queue %d state : %lld\n", prio, rc); |
|
return -EIO; |
|
} |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_set_queue_state); |
|
|
|
bool xive_native_has_queue_state_support(void) |
|
{ |
|
return opal_check_token(OPAL_XIVE_GET_QUEUE_STATE) && |
|
opal_check_token(OPAL_XIVE_SET_QUEUE_STATE); |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_has_queue_state_support); |
|
|
|
int xive_native_get_vp_state(u32 vp_id, u64 *out_state) |
|
{ |
|
__be64 state; |
|
s64 rc; |
|
|
|
rc = opal_xive_get_vp_state(vp_id, &state); |
|
if (rc) { |
|
vp_err(vp_id, "failed to get vp state : %lld\n", rc); |
|
return -EIO; |
|
} |
|
|
|
if (out_state) |
|
*out_state = be64_to_cpu(state); |
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xive_native_get_vp_state); |
|
|
|
machine_arch_initcall(powernv, xive_core_debug_init);
|
|
|