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442 lines
11 KiB
442 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* arch/powerpc/sysdev/dart_iommu.c |
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* |
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* Copyright (C) 2004 Olof Johansson <[email protected]>, IBM Corporation |
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* Copyright (C) 2005 Benjamin Herrenschmidt <[email protected]>, |
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* IBM Corporation |
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* |
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* Based on pSeries_iommu.c: |
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
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* Copyright (C) 2004 Olof Johansson <[email protected]>, IBM Corporation |
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* |
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* Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. |
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*/ |
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#include <linux/init.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/spinlock.h> |
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#include <linux/string.h> |
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#include <linux/pci.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/vmalloc.h> |
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#include <linux/suspend.h> |
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#include <linux/memblock.h> |
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#include <linux/gfp.h> |
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#include <linux/kmemleak.h> |
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#include <asm/io.h> |
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#include <asm/prom.h> |
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#include <asm/iommu.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/machdep.h> |
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#include <asm/cacheflush.h> |
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#include <asm/ppc-pci.h> |
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#include "dart.h" |
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/* DART table address and size */ |
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static u32 *dart_tablebase; |
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static unsigned long dart_tablesize; |
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/* Mapped base address for the dart */ |
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static unsigned int __iomem *dart; |
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/* Dummy val that entries are set to when unused */ |
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static unsigned int dart_emptyval; |
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static struct iommu_table iommu_table_dart; |
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static int iommu_table_dart_inited; |
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static int dart_dirty; |
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static int dart_is_u4; |
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#define DART_U4_BYPASS_BASE 0x8000000000ull |
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#define DBG(...) |
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static DEFINE_SPINLOCK(invalidate_lock); |
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static inline void dart_tlb_invalidate_all(void) |
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{ |
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unsigned long l = 0; |
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unsigned int reg, inv_bit; |
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unsigned long limit; |
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unsigned long flags; |
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spin_lock_irqsave(&invalidate_lock, flags); |
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DBG("dart: flush\n"); |
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/* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the |
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* control register and wait for it to clear. |
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* |
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* Gotcha: Sometimes, the DART won't detect that the bit gets |
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* set. If so, clear it and set it again. |
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*/ |
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limit = 0; |
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inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; |
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retry: |
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l = 0; |
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reg = DART_IN(DART_CNTL); |
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reg |= inv_bit; |
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DART_OUT(DART_CNTL, reg); |
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while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) |
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l++; |
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if (l == (1L << limit)) { |
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if (limit < 4) { |
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limit++; |
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reg = DART_IN(DART_CNTL); |
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reg &= ~inv_bit; |
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DART_OUT(DART_CNTL, reg); |
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goto retry; |
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} else |
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panic("DART: TLB did not flush after waiting a long " |
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"time. Buggy U3 ?"); |
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} |
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spin_unlock_irqrestore(&invalidate_lock, flags); |
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} |
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static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) |
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{ |
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unsigned int reg; |
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unsigned int l, limit; |
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unsigned long flags; |
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spin_lock_irqsave(&invalidate_lock, flags); |
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reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | |
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(bus_rpn & DART_CNTL_U4_IONE_MASK); |
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DART_OUT(DART_CNTL, reg); |
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limit = 0; |
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wait_more: |
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l = 0; |
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while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { |
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rmb(); |
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l++; |
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} |
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if (l == (1L << limit)) { |
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if (limit < 4) { |
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limit++; |
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goto wait_more; |
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} else |
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panic("DART: TLB did not flush after waiting a long " |
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"time. Buggy U4 ?"); |
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} |
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spin_unlock_irqrestore(&invalidate_lock, flags); |
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} |
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static void dart_cache_sync(unsigned int *base, unsigned int count) |
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{ |
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/* |
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* We add 1 to the number of entries to flush, following a |
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* comment in Darwin indicating that the memory controller |
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* can prefetch unmapped memory under some circumstances. |
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*/ |
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unsigned long start = (unsigned long)base; |
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unsigned long end = start + (count + 1) * sizeof(unsigned int); |
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unsigned int tmp; |
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/* Perform a standard cache flush */ |
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flush_dcache_range(start, end); |
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/* |
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* Perform the sequence described in the CPC925 manual to |
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* ensure all the data gets to a point the cache incoherent |
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* DART hardware will see. |
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*/ |
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asm volatile(" sync;" |
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" isync;" |
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" dcbf 0,%1;" |
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" sync;" |
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" isync;" |
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" lwz %0,0(%1);" |
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" isync" : "=r" (tmp) : "r" (end) : "memory"); |
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} |
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static void dart_flush(struct iommu_table *tbl) |
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{ |
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mb(); |
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if (dart_dirty) { |
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dart_tlb_invalidate_all(); |
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dart_dirty = 0; |
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} |
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} |
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static int dart_build(struct iommu_table *tbl, long index, |
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long npages, unsigned long uaddr, |
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enum dma_data_direction direction, |
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unsigned long attrs) |
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{ |
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unsigned int *dp, *orig_dp; |
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unsigned int rpn; |
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long l; |
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DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); |
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orig_dp = dp = ((unsigned int*)tbl->it_base) + index; |
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/* On U3, all memory is contiguous, so we can move this |
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* out of the loop. |
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*/ |
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l = npages; |
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while (l--) { |
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rpn = __pa(uaddr) >> DART_PAGE_SHIFT; |
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*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); |
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uaddr += DART_PAGE_SIZE; |
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} |
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dart_cache_sync(orig_dp, npages); |
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if (dart_is_u4) { |
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rpn = index; |
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while (npages--) |
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dart_tlb_invalidate_one(rpn++); |
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} else { |
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dart_dirty = 1; |
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} |
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return 0; |
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} |
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static void dart_free(struct iommu_table *tbl, long index, long npages) |
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{ |
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unsigned int *dp, *orig_dp; |
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long orig_npages = npages; |
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/* We don't worry about flushing the TLB cache. The only drawback of |
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* not doing it is that we won't catch buggy device drivers doing |
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* bad DMAs, but then no 32-bit architecture ever does either. |
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*/ |
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DBG("dart: free at: %lx, %lx\n", index, npages); |
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orig_dp = dp = ((unsigned int *)tbl->it_base) + index; |
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while (npages--) |
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*(dp++) = dart_emptyval; |
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dart_cache_sync(orig_dp, orig_npages); |
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} |
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static void allocate_dart(void) |
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{ |
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unsigned long tmp; |
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/* 512 pages (2MB) is max DART tablesize. */ |
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dart_tablesize = 1UL << 21; |
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/* |
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* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we |
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* will blow up an entire large page anyway in the kernel mapping. |
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*/ |
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dart_tablebase = memblock_alloc_try_nid_raw(SZ_16M, SZ_16M, |
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MEMBLOCK_LOW_LIMIT, SZ_2G, |
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NUMA_NO_NODE); |
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if (!dart_tablebase) |
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panic("Failed to allocate 16MB below 2GB for DART table\n"); |
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/* There is no point scanning the DART space for leaks*/ |
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kmemleak_no_scan((void *)dart_tablebase); |
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/* Allocate a spare page to map all invalid DART pages. We need to do |
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* that to work around what looks like a problem with the HT bridge |
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* prefetching into invalid pages and corrupting data |
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*/ |
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tmp = memblock_phys_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
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if (!tmp) |
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panic("DART: table allocation failed\n"); |
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dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & |
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DARTMAP_RPNMASK); |
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printk(KERN_INFO "DART table allocated at: %p\n", dart_tablebase); |
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} |
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static int __init dart_init(struct device_node *dart_node) |
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{ |
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unsigned int i; |
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unsigned long base, size; |
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struct resource r; |
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/* IOMMU disabled by the user ? bail out */ |
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if (iommu_is_off) |
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return -ENODEV; |
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/* |
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* Only use the DART if the machine has more than 1GB of RAM |
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* or if requested with iommu=on on cmdline. |
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* |
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* 1GB of RAM is picked as limit because some default devices |
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* (i.e. Airport Extreme) have 30 bit address range limits. |
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*/ |
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if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull) |
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return -ENODEV; |
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/* Get DART registers */ |
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if (of_address_to_resource(dart_node, 0, &r)) |
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panic("DART: can't get register base ! "); |
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/* Map in DART registers */ |
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dart = ioremap(r.start, resource_size(&r)); |
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if (dart == NULL) |
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panic("DART: Cannot map registers!"); |
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/* Allocate the DART and dummy page */ |
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allocate_dart(); |
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/* Fill initial table */ |
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for (i = 0; i < dart_tablesize/4; i++) |
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dart_tablebase[i] = dart_emptyval; |
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/* Push to memory */ |
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dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32)); |
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/* Initialize DART with table base and enable it. */ |
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base = ((unsigned long)dart_tablebase) >> DART_PAGE_SHIFT; |
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size = dart_tablesize >> DART_PAGE_SHIFT; |
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if (dart_is_u4) { |
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size &= DART_SIZE_U4_SIZE_MASK; |
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DART_OUT(DART_BASE_U4, base); |
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DART_OUT(DART_SIZE_U4, size); |
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DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); |
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} else { |
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size &= DART_CNTL_U3_SIZE_MASK; |
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DART_OUT(DART_CNTL, |
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DART_CNTL_U3_ENABLE | |
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(base << DART_CNTL_U3_BASE_SHIFT) | |
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(size << DART_CNTL_U3_SIZE_SHIFT)); |
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} |
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/* Invalidate DART to get rid of possible stale TLBs */ |
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dart_tlb_invalidate_all(); |
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printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", |
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dart_is_u4 ? "U4" : "U3"); |
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return 0; |
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} |
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static struct iommu_table_ops iommu_dart_ops = { |
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.set = dart_build, |
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.clear = dart_free, |
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.flush = dart_flush, |
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}; |
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static void iommu_table_dart_setup(void) |
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{ |
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iommu_table_dart.it_busno = 0; |
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iommu_table_dart.it_offset = 0; |
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/* it_size is in number of entries */ |
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iommu_table_dart.it_size = dart_tablesize / sizeof(u32); |
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iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K; |
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/* Initialize the common IOMMU code */ |
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iommu_table_dart.it_base = (unsigned long)dart_tablebase; |
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iommu_table_dart.it_index = 0; |
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iommu_table_dart.it_blocksize = 1; |
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iommu_table_dart.it_ops = &iommu_dart_ops; |
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if (!iommu_init_table(&iommu_table_dart, -1, 0, 0)) |
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panic("Failed to initialize iommu table"); |
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/* Reserve the last page of the DART to avoid possible prefetch |
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* past the DART mapped area |
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*/ |
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set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); |
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} |
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static void pci_dma_bus_setup_dart(struct pci_bus *bus) |
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{ |
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if (!iommu_table_dart_inited) { |
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iommu_table_dart_inited = 1; |
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iommu_table_dart_setup(); |
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} |
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} |
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static bool dart_device_on_pcie(struct device *dev) |
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{ |
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struct device_node *np = of_node_get(dev->of_node); |
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while(np) { |
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if (of_device_is_compatible(np, "U4-pcie") || |
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of_device_is_compatible(np, "u4-pcie")) { |
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of_node_put(np); |
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return true; |
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} |
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np = of_get_next_parent(np); |
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} |
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return false; |
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} |
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static void pci_dma_dev_setup_dart(struct pci_dev *dev) |
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{ |
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if (dart_is_u4 && dart_device_on_pcie(&dev->dev)) |
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dev->dev.archdata.dma_offset = DART_U4_BYPASS_BASE; |
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set_iommu_table_base(&dev->dev, &iommu_table_dart); |
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} |
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static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask) |
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{ |
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return dart_is_u4 && |
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dart_device_on_pcie(&dev->dev) && |
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mask >= DMA_BIT_MASK(40); |
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} |
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void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops) |
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{ |
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struct device_node *dn; |
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/* Find the DART in the device-tree */ |
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dn = of_find_compatible_node(NULL, "dart", "u3-dart"); |
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if (dn == NULL) { |
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dn = of_find_compatible_node(NULL, "dart", "u4-dart"); |
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if (dn == NULL) |
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return; /* use default direct_dma_ops */ |
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dart_is_u4 = 1; |
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} |
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/* Initialize the DART HW */ |
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if (dart_init(dn) != 0) |
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return; |
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/* |
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* U4 supports a DART bypass, we use it for 64-bit capable devices to |
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* improve performance. However, that only works for devices connected |
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* to the U4 own PCIe interface, not bridged through hypertransport. |
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* We need the device to support at least 40 bits of addresses. |
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*/ |
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controller_ops->dma_dev_setup = pci_dma_dev_setup_dart; |
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controller_ops->dma_bus_setup = pci_dma_bus_setup_dart; |
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controller_ops->iommu_bypass_supported = iommu_bypass_supported_dart; |
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/* Setup pci_dma ops */ |
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set_pci_dma_ops(&dma_iommu_ops); |
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} |
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#ifdef CONFIG_PM |
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static void iommu_dart_restore(void) |
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{ |
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dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32)); |
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dart_tlb_invalidate_all(); |
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} |
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static int __init iommu_init_late_dart(void) |
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{ |
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if (!dart_tablebase) |
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return 0; |
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ppc_md.iommu_restore = iommu_dart_restore; |
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return 0; |
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} |
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late_initcall(iommu_init_late_dart); |
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#endif /* CONFIG_PM */
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