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500 lines
11 KiB
500 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* This file contains kexec low-level functions. |
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* |
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* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> |
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* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz |
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* PPC44x port. Copyright (C) 2011, IBM Corporation |
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* Author: Suzuki Poulose <suzuki@in.ibm.com> |
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*/ |
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#include <asm/reg.h> |
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#include <asm/page.h> |
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#include <asm/mmu.h> |
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#include <asm/ppc_asm.h> |
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#include <asm/kexec.h> |
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.text |
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/* |
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* Must be relocatable PIC code callable as a C function. |
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*/ |
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.globl relocate_new_kernel |
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relocate_new_kernel: |
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/* r3 = page_list */ |
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/* r4 = reboot_code_buffer */ |
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/* r5 = start_address */ |
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#ifdef CONFIG_FSL_BOOKE |
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mr r29, r3 |
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mr r30, r4 |
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mr r31, r5 |
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#define ENTRY_MAPPING_KEXEC_SETUP |
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#include <kernel/fsl_booke_entry_mapping.S> |
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#undef ENTRY_MAPPING_KEXEC_SETUP |
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mr r3, r29 |
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mr r4, r30 |
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mr r5, r31 |
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li r0, 0 |
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#elif defined(CONFIG_44x) |
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/* Save our parameters */ |
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mr r29, r3 |
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mr r30, r4 |
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mr r31, r5 |
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#ifdef CONFIG_PPC_47x |
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/* Check for 47x cores */ |
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mfspr r3,SPRN_PVR |
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srwi r3,r3,16 |
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cmplwi cr0,r3,PVR_476FPE@h |
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beq setup_map_47x |
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cmplwi cr0,r3,PVR_476@h |
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beq setup_map_47x |
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cmplwi cr0,r3,PVR_476_ISS@h |
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beq setup_map_47x |
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#endif /* CONFIG_PPC_47x */ |
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/* |
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* Code for setting up 1:1 mapping for PPC440x for KEXEC |
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* |
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* We cannot switch off the MMU on PPC44x. |
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* So we: |
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* 1) Invalidate all the mappings except the one we are running from. |
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* 2) Create a tmp mapping for our code in the other address space(TS) and |
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* jump to it. Invalidate the entry we started in. |
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* 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS. |
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* 4) Jump to the 1:1 mapping in original TS. |
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* 5) Invalidate the tmp mapping. |
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* |
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* - Based on the kexec support code for FSL BookE |
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* |
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*/ |
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/* |
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* Load the PID with kernel PID (0). |
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* Also load our MSR_IS and TID to MMUCR for TLB search. |
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*/ |
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li r3, 0 |
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mtspr SPRN_PID, r3 |
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mfmsr r4 |
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andi. r4,r4,MSR_IS@l |
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beq wmmucr |
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oris r3,r3,PPC44x_MMUCR_STS@h |
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wmmucr: |
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mtspr SPRN_MMUCR,r3 |
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sync |
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/* |
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* Invalidate all the TLB entries except the current entry |
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* where we are running from |
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*/ |
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bcl 20,31,$+4 /* Find our address */ |
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0: mflr r5 /* Make it accessible */ |
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tlbsx r23,0,r5 /* Find entry we are in */ |
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li r4,0 /* Start at TLB entry 0 */ |
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li r3,0 /* Set PAGEID inval value */ |
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1: cmpw r23,r4 /* Is this our entry? */ |
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beq skip /* If so, skip the inval */ |
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tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ |
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skip: |
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addi r4,r4,1 /* Increment */ |
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cmpwi r4,64 /* Are we done? */ |
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bne 1b /* If not, repeat */ |
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isync |
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/* Create a temp mapping and jump to it */ |
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andi. r6, r23, 1 /* Find the index to use */ |
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addi r24, r6, 1 /* r24 will contain 1 or 2 */ |
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mfmsr r9 /* get the MSR */ |
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rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */ |
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xori r7, r5, 1 /* Use the other address space */ |
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/* Read the current mapping entries */ |
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tlbre r3, r23, PPC44x_TLB_PAGEID |
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tlbre r4, r23, PPC44x_TLB_XLAT |
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tlbre r5, r23, PPC44x_TLB_ATTRIB |
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/* Save our current XLAT entry */ |
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mr r25, r4 |
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/* Extract the TLB PageSize */ |
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li r10, 1 /* r10 will hold PageSize */ |
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rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */ |
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/* XXX: As of now we use 256M, 4K pages */ |
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cmpwi r11, PPC44x_TLB_256M |
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bne tlb_4k |
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rotlwi r10, r10, 28 /* r10 = 256M */ |
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b write_out |
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tlb_4k: |
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cmpwi r11, PPC44x_TLB_4K |
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bne default |
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rotlwi r10, r10, 12 /* r10 = 4K */ |
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b write_out |
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default: |
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rotlwi r10, r10, 10 /* r10 = 1K */ |
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write_out: |
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/* |
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* Write out the tmp 1:1 mapping for this code in other address space |
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* Fixup EPN = RPN , TS=other address space |
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*/ |
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insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */ |
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/* Write out the tmp mapping entries */ |
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tlbwe r3, r24, PPC44x_TLB_PAGEID |
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tlbwe r4, r24, PPC44x_TLB_XLAT |
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tlbwe r5, r24, PPC44x_TLB_ATTRIB |
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subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */ |
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not r10, r11 /* Mask for PageNum */ |
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/* Switch to other address space in MSR */ |
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insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ |
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bcl 20,31,$+4 |
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1: mflr r8 |
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addi r8, r8, (2f-1b) /* Find the target offset */ |
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/* Jump to the tmp mapping */ |
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mtspr SPRN_SRR0, r8 |
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mtspr SPRN_SRR1, r9 |
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rfi |
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2: |
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/* Invalidate the entry we were executing from */ |
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li r3, 0 |
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tlbwe r3, r23, PPC44x_TLB_PAGEID |
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/* attribute fields. rwx for SUPERVISOR mode */ |
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li r5, 0 |
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ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) |
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/* Create 1:1 mapping in 256M pages */ |
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xori r7, r7, 1 /* Revert back to Original TS */ |
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li r8, 0 /* PageNumber */ |
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li r6, 3 /* TLB Index, start at 3 */ |
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next_tlb: |
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rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */ |
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mr r4, r3 /* RPN = EPN */ |
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ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */ |
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insrwi r3, r7, 1, 23 /* Set TS from r7 */ |
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tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */ |
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tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */ |
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tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */ |
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addi r8, r8, 1 /* Increment PN */ |
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addi r6, r6, 1 /* Increment TLB Index */ |
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cmpwi r8, 8 /* Are we done ? */ |
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bne next_tlb |
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isync |
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/* Jump to the new mapping 1:1 */ |
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li r9,0 |
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insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */ |
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bcl 20,31,$+4 |
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1: mflr r8 |
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and r8, r8, r11 /* Get our offset within page */ |
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addi r8, r8, (2f-1b) |
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and r5, r25, r10 /* Get our target PageNum */ |
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or r8, r8, r5 /* Target jump address */ |
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mtspr SPRN_SRR0, r8 |
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mtspr SPRN_SRR1, r9 |
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rfi |
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2: |
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/* Invalidate the tmp entry we used */ |
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li r3, 0 |
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tlbwe r3, r24, PPC44x_TLB_PAGEID |
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sync |
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b ppc44x_map_done |
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#ifdef CONFIG_PPC_47x |
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/* 1:1 mapping for 47x */ |
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setup_map_47x: |
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/* |
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* Load the kernel pid (0) to PID and also to MMUCR[TID]. |
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* Also set the MSR IS->MMUCR STS |
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*/ |
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li r3, 0 |
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mtspr SPRN_PID, r3 /* Set PID */ |
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mfmsr r4 /* Get MSR */ |
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andi. r4, r4, MSR_IS@l /* TS=1? */ |
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beq 1f /* If not, leave STS=0 */ |
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oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */ |
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1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */ |
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sync |
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/* Find the entry we are running from */ |
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bcl 20,31,$+4 |
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2: mflr r23 |
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tlbsx r23, 0, r23 |
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tlbre r24, r23, 0 /* TLB Word 0 */ |
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tlbre r25, r23, 1 /* TLB Word 1 */ |
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tlbre r26, r23, 2 /* TLB Word 2 */ |
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/* |
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* Invalidates all the tlb entries by writing to 256 RPNs(r4) |
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* of 4k page size in all 4 ways (0-3 in r3). |
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* This would invalidate the entire UTLB including the one we are |
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* running from. However the shadow TLB entries would help us |
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* to continue the execution, until we flush them (rfi/isync). |
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*/ |
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addis r3, 0, 0x8000 /* specify the way */ |
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addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */ |
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addi r5, 0, 0 |
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b clear_utlb_entry |
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/* Align the loop to speed things up. from head_44x.S */ |
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.align 6 |
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clear_utlb_entry: |
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tlbwe r4, r3, 0 |
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tlbwe r5, r3, 1 |
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tlbwe r5, r3, 2 |
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addis r3, r3, 0x2000 /* Increment the way */ |
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cmpwi r3, 0 |
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bne clear_utlb_entry |
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addis r3, 0, 0x8000 |
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addis r4, r4, 0x100 /* Increment the EPN */ |
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cmpwi r4, 0 |
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bne clear_utlb_entry |
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/* Create the entries in the other address space */ |
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mfmsr r5 |
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rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */ |
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xori r7, r7, 1 /* r7 = !TS */ |
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insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */ |
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/* |
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* write out the TLB entries for the tmp mapping |
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* Use way '0' so that we could easily invalidate it later. |
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*/ |
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lis r3, 0x8000 /* Way '0' */ |
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tlbwe r24, r3, 0 |
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tlbwe r25, r3, 1 |
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tlbwe r26, r3, 2 |
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/* Update the msr to the new TS */ |
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insrwi r5, r7, 1, 26 |
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bcl 20,31,$+4 |
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1: mflr r6 |
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addi r6, r6, (2f-1b) |
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mtspr SPRN_SRR0, r6 |
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mtspr SPRN_SRR1, r5 |
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rfi |
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/* |
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* Now we are in the tmp address space. |
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* Create a 1:1 mapping for 0-2GiB in the original TS. |
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*/ |
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2: |
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li r3, 0 |
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li r4, 0 /* TLB Word 0 */ |
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li r5, 0 /* TLB Word 1 */ |
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li r6, 0 |
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ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */ |
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li r8, 0 /* PageIndex */ |
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xori r7, r7, 1 /* revert back to original TS */ |
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write_utlb: |
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rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */ |
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/* ERPN = 0 as we don't use memory above 2G */ |
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mr r4, r5 /* EPN = RPN */ |
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ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M) |
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insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */ |
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tlbwe r4, r3, 0 /* Write out the entries */ |
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tlbwe r5, r3, 1 |
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tlbwe r6, r3, 2 |
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addi r8, r8, 1 |
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cmpwi r8, 8 /* Have we completed ? */ |
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bne write_utlb |
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/* make sure we complete the TLB write up */ |
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isync |
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/* |
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* Prepare to jump to the 1:1 mapping. |
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* 1) Extract page size of the tmp mapping |
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* DSIZ = TLB_Word0[22:27] |
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* 2) Calculate the physical address of the address |
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* to jump to. |
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*/ |
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rlwinm r10, r24, 0, 22, 27 |
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cmpwi r10, PPC47x_TLB0_4K |
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bne 0f |
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li r10, 0x1000 /* r10 = 4k */ |
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bl 1f |
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0: |
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/* Defaults to 256M */ |
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lis r10, 0x1000 |
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bcl 20,31,$+4 |
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1: mflr r4 |
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addi r4, r4, (2f-1b) /* virtual address of 2f */ |
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subi r11, r10, 1 /* offsetmask = Pagesize - 1 */ |
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not r10, r11 /* Pagemask = ~(offsetmask) */ |
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and r5, r25, r10 /* Physical page */ |
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and r6, r4, r11 /* offset within the current page */ |
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or r5, r5, r6 /* Physical address for 2f */ |
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/* Switch the TS in MSR to the original one */ |
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mfmsr r8 |
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insrwi r8, r7, 1, 26 |
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mtspr SPRN_SRR1, r8 |
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mtspr SPRN_SRR0, r5 |
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rfi |
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2: |
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/* Invalidate the tmp mapping */ |
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lis r3, 0x8000 /* Way '0' */ |
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clrrwi r24, r24, 12 /* Clear the valid bit */ |
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tlbwe r24, r3, 0 |
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tlbwe r25, r3, 1 |
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tlbwe r26, r3, 2 |
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/* Make sure we complete the TLB write and flush the shadow TLB */ |
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isync |
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#endif |
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ppc44x_map_done: |
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/* Restore the parameters */ |
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mr r3, r29 |
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mr r4, r30 |
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mr r5, r31 |
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li r0, 0 |
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#else |
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li r0, 0 |
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/* |
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* Set Machine Status Register to a known status, |
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* switch the MMU off and jump to 1: in a single step. |
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*/ |
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mr r8, r0 |
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ori r8, r8, MSR_RI|MSR_ME |
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mtspr SPRN_SRR1, r8 |
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addi r8, r4, 1f - relocate_new_kernel |
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mtspr SPRN_SRR0, r8 |
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sync |
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rfi |
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1: |
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#endif |
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/* from this point address translation is turned off */ |
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/* and interrupts are disabled */ |
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/* set a new stack at the bottom of our page... */ |
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/* (not really needed now) */ |
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addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */ |
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stw r0, 0(r1) |
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/* Do the copies */ |
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li r6, 0 /* checksum */ |
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mr r0, r3 |
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b 1f |
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0: /* top, read another word for the indirection page */ |
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lwzu r0, 4(r3) |
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1: |
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/* is it a destination page? (r8) */ |
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rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ |
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beq 2f |
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rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ |
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b 0b |
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2: /* is it an indirection page? (r3) */ |
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rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ |
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beq 2f |
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rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ |
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subi r3, r3, 4 |
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b 0b |
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2: /* are we done? */ |
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rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ |
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beq 2f |
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b 3f |
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2: /* is it a source page? (r9) */ |
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rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ |
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beq 0b |
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rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ |
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li r7, PAGE_SIZE / 4 |
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mtctr r7 |
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subi r9, r9, 4 |
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subi r8, r8, 4 |
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9: |
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lwzu r0, 4(r9) /* do the copy */ |
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xor r6, r6, r0 |
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stwu r0, 4(r8) |
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dcbst 0, r8 |
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sync |
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icbi 0, r8 |
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bdnz 9b |
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addi r9, r9, 4 |
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addi r8, r8, 4 |
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b 0b |
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3: |
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/* To be certain of avoiding problems with self-modifying code |
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* execute a serializing instruction here. |
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*/ |
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isync |
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sync |
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mfspr r3, SPRN_PIR /* current core we are running on */ |
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mr r4, r5 /* load physical address of chunk called */ |
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/* jump to the entry point, usually the setup routine */ |
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mtlr r5 |
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blrl |
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1: b 1b |
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relocate_new_kernel_end: |
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.globl relocate_new_kernel_size |
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relocate_new_kernel_size: |
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.long relocate_new_kernel_end - relocate_new_kernel
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