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736 lines
24 KiB
736 lines
24 KiB
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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/* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, version 2, as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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* |
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* Copyright IBM Corp. 2007 |
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* |
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* Authors: Hollis Blanchard <[email protected]> |
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*/ |
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#ifndef __LINUX_KVM_POWERPC_H |
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#define __LINUX_KVM_POWERPC_H |
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#include <linux/types.h> |
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/* Select powerpc specific features in <linux/kvm.h> */ |
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#define __KVM_HAVE_SPAPR_TCE |
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#define __KVM_HAVE_PPC_SMT |
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#define __KVM_HAVE_IRQCHIP |
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#define __KVM_HAVE_IRQ_LINE |
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#define __KVM_HAVE_GUEST_DEBUG |
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/* Not always available, but if it is, this is the correct offset. */ |
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 |
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struct kvm_regs { |
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__u64 pc; |
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__u64 cr; |
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__u64 ctr; |
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__u64 lr; |
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__u64 xer; |
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__u64 msr; |
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__u64 srr0; |
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__u64 srr1; |
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__u64 pid; |
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__u64 sprg0; |
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__u64 sprg1; |
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__u64 sprg2; |
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__u64 sprg3; |
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__u64 sprg4; |
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__u64 sprg5; |
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__u64 sprg6; |
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__u64 sprg7; |
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__u64 gpr[32]; |
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}; |
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#define KVM_SREGS_E_IMPL_NONE 0 |
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#define KVM_SREGS_E_IMPL_FSL 1 |
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#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */ |
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/* flags for kvm_run.flags */ |
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#define KVM_RUN_PPC_NMI_DISP_MASK (3 << 0) |
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#define KVM_RUN_PPC_NMI_DISP_FULLY_RECOV (1 << 0) |
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#define KVM_RUN_PPC_NMI_DISP_LIMITED_RECOV (2 << 0) |
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#define KVM_RUN_PPC_NMI_DISP_NOT_RECOV (3 << 0) |
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/* |
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* Feature bits indicate which sections of the sregs struct are valid, |
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* both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers |
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* corresponding to unset feature bits will not be modified. This allows |
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* restoring a checkpoint made without that feature, while keeping the |
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* default values of the new registers. |
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* |
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* KVM_SREGS_E_BASE contains: |
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* CSRR0/1 (refers to SRR2/3 on 40x) |
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* ESR |
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* DEAR |
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* MCSR |
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* TSR |
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* TCR |
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* DEC |
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* TB |
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* VRSAVE (USPRG0) |
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*/ |
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#define KVM_SREGS_E_BASE (1 << 0) |
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/* |
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* KVM_SREGS_E_ARCH206 contains: |
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* |
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* PIR |
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* MCSRR0/1 |
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* DECAR |
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* IVPR |
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*/ |
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#define KVM_SREGS_E_ARCH206 (1 << 1) |
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/* |
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* Contains EPCR, plus the upper half of 64-bit registers |
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* that are 32-bit on 32-bit implementations. |
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*/ |
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#define KVM_SREGS_E_64 (1 << 2) |
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#define KVM_SREGS_E_SPRG8 (1 << 3) |
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#define KVM_SREGS_E_MCIVPR (1 << 4) |
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/* |
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* IVORs are used -- contains IVOR0-15, plus additional IVORs |
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* in combination with an appropriate feature bit. |
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*/ |
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#define KVM_SREGS_E_IVOR (1 << 5) |
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/* |
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* Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG. |
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* Also TLBnPS if MMUCFG[MAVN] = 1. |
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*/ |
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#define KVM_SREGS_E_ARCH206_MMU (1 << 6) |
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/* DBSR, DBCR, IAC, DAC, DVC */ |
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#define KVM_SREGS_E_DEBUG (1 << 7) |
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/* Enhanced debug -- DSRR0/1, SPRG9 */ |
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#define KVM_SREGS_E_ED (1 << 8) |
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/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */ |
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#define KVM_SREGS_E_SPE (1 << 9) |
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/* |
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* DEPRECATED! USE ONE_REG FOR THIS ONE! |
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* External Proxy (EXP) -- EPR |
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*/ |
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#define KVM_SREGS_EXP (1 << 10) |
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/* External PID (E.PD) -- EPSC/EPLC */ |
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#define KVM_SREGS_E_PD (1 << 11) |
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/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */ |
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#define KVM_SREGS_E_PC (1 << 12) |
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/* Page table (E.PT) -- EPTCFG */ |
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#define KVM_SREGS_E_PT (1 << 13) |
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/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */ |
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#define KVM_SREGS_E_PM (1 << 14) |
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/* |
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* Special updates: |
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* |
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* Some registers may change even while a vcpu is not running. |
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* To avoid losing these changes, by default these registers are |
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* not updated by KVM_SET_SREGS. To force an update, set the bit |
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* in u.e.update_special corresponding to the register to be updated. |
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* |
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* The update_special field is zero on return from KVM_GET_SREGS. |
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* |
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* When restoring a checkpoint, the caller can set update_special |
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* to 0xffffffff to ensure that everything is restored, even new features |
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* that the caller doesn't know about. |
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*/ |
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#define KVM_SREGS_E_UPDATE_MCSR (1 << 0) |
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#define KVM_SREGS_E_UPDATE_TSR (1 << 1) |
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#define KVM_SREGS_E_UPDATE_DEC (1 << 2) |
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#define KVM_SREGS_E_UPDATE_DBSR (1 << 3) |
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/* |
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* In KVM_SET_SREGS, reserved/pad fields must be left untouched from a |
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* previous KVM_GET_REGS. |
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* |
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* Unless otherwise indicated, setting any register with KVM_SET_SREGS |
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* directly sets its value. It does not trigger any special semantics such |
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* as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct |
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* just received from KVM_GET_SREGS is always a no-op. |
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*/ |
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struct kvm_sregs { |
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__u32 pvr; |
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union { |
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struct { |
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__u64 sdr1; |
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struct { |
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struct { |
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__u64 slbe; |
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__u64 slbv; |
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} slb[64]; |
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} ppc64; |
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struct { |
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__u32 sr[16]; |
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__u64 ibat[8]; |
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__u64 dbat[8]; |
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} ppc32; |
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} s; |
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struct { |
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union { |
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struct { /* KVM_SREGS_E_IMPL_FSL */ |
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__u32 features; /* KVM_SREGS_E_FSL_ */ |
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__u32 svr; |
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__u64 mcar; |
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__u32 hid0; |
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/* KVM_SREGS_E_FSL_PIDn */ |
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__u32 pid1, pid2; |
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} fsl; |
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__u8 pad[256]; |
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} impl; |
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__u32 features; /* KVM_SREGS_E_ */ |
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__u32 impl_id; /* KVM_SREGS_E_IMPL_ */ |
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__u32 update_special; /* KVM_SREGS_E_UPDATE_ */ |
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__u32 pir; /* read-only */ |
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__u64 sprg8; |
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__u64 sprg9; /* E.ED */ |
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__u64 csrr0; |
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__u64 dsrr0; /* E.ED */ |
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__u64 mcsrr0; |
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__u32 csrr1; |
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__u32 dsrr1; /* E.ED */ |
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__u32 mcsrr1; |
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__u32 esr; |
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__u64 dear; |
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__u64 ivpr; |
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__u64 mcivpr; |
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__u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */ |
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__u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */ |
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__u32 tcr; |
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__u32 decar; |
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__u32 dec; /* KVM_SREGS_E_UPDATE_DEC */ |
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/* |
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* Userspace can read TB directly, but the |
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* value reported here is consistent with "dec". |
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* |
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* Read-only. |
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*/ |
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__u64 tb; |
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__u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */ |
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__u32 dbcr[3]; |
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/* |
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* iac/dac registers are 64bit wide, while this API |
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* interface provides only lower 32 bits on 64 bit |
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* processors. ONE_REG interface is added for 64bit |
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* iac/dac registers. |
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*/ |
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__u32 iac[4]; |
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__u32 dac[2]; |
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__u32 dvc[2]; |
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__u8 num_iac; /* read-only */ |
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__u8 num_dac; /* read-only */ |
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__u8 num_dvc; /* read-only */ |
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__u8 pad; |
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__u32 epr; /* EXP */ |
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__u32 vrsave; /* a.k.a. USPRG0 */ |
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__u32 epcr; /* KVM_SREGS_E_64 */ |
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__u32 mas0; |
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__u32 mas1; |
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__u64 mas2; |
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__u64 mas7_3; |
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__u32 mas4; |
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__u32 mas6; |
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__u32 ivor_low[16]; /* IVOR0-15 */ |
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__u32 ivor_high[18]; /* IVOR32+, plus room to expand */ |
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__u32 mmucfg; /* read-only */ |
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__u32 eptcfg; /* E.PT, read-only */ |
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__u32 tlbcfg[4];/* read-only */ |
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__u32 tlbps[4]; /* read-only */ |
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__u32 eplc, epsc; /* E.PD */ |
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} e; |
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__u8 pad[1020]; |
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} u; |
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}; |
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struct kvm_fpu { |
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__u64 fpr[32]; |
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}; |
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/* |
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* Defines for h/w breakpoint, watchpoint (read, write or both) and |
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* software breakpoint. |
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* These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status" |
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* for KVM_DEBUG_EXIT. |
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*/ |
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#define KVMPPC_DEBUG_NONE 0x0 |
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#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1) |
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#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2) |
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#define KVMPPC_DEBUG_WATCH_READ (1UL << 3) |
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struct kvm_debug_exit_arch { |
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__u64 address; |
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/* |
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* exiting to userspace because of h/w breakpoint, watchpoint |
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* (read, write or both) and software breakpoint. |
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*/ |
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__u32 status; |
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__u32 reserved; |
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}; |
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/* for KVM_SET_GUEST_DEBUG */ |
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struct kvm_guest_debug_arch { |
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struct { |
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/* H/W breakpoint/watchpoint address */ |
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__u64 addr; |
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/* |
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* Type denotes h/w breakpoint, read watchpoint, write |
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* watchpoint or watchpoint (both read and write). |
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*/ |
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__u32 type; |
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__u32 reserved; |
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} bp[16]; |
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}; |
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/* Debug related defines */ |
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/* |
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* kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic |
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* and upper 16 bits are architecture specific. Architecture specific defines |
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* that ioctl is for setting hardware breakpoint or software breakpoint. |
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*/ |
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#define KVM_GUESTDBG_USE_SW_BP 0x00010000 |
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#define KVM_GUESTDBG_USE_HW_BP 0x00020000 |
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/* definition of registers in kvm_run */ |
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struct kvm_sync_regs { |
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}; |
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#define KVM_INTERRUPT_SET -1U |
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#define KVM_INTERRUPT_UNSET -2U |
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#define KVM_INTERRUPT_SET_LEVEL -3U |
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#define KVM_CPU_440 1 |
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#define KVM_CPU_E500V2 2 |
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#define KVM_CPU_3S_32 3 |
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#define KVM_CPU_3S_64 4 |
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#define KVM_CPU_E500MC 5 |
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/* for KVM_CAP_SPAPR_TCE */ |
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struct kvm_create_spapr_tce { |
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__u64 liobn; |
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__u32 window_size; |
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}; |
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/* for KVM_CAP_SPAPR_TCE_64 */ |
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struct kvm_create_spapr_tce_64 { |
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__u64 liobn; |
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__u32 page_shift; |
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__u32 flags; |
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__u64 offset; /* in pages */ |
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__u64 size; /* in pages */ |
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}; |
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/* for KVM_ALLOCATE_RMA */ |
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struct kvm_allocate_rma { |
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__u64 rma_size; |
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}; |
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/* for KVM_CAP_PPC_RTAS */ |
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struct kvm_rtas_token_args { |
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char name[120]; |
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__u64 token; /* Use a token of 0 to undefine a mapping */ |
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}; |
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struct kvm_book3e_206_tlb_entry { |
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__u32 mas8; |
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__u32 mas1; |
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__u64 mas2; |
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__u64 mas7_3; |
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}; |
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struct kvm_book3e_206_tlb_params { |
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/* |
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* For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV: |
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* |
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* - The number of ways of TLB0 must be a power of two between 2 and |
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* 16. |
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* - TLB1 must be fully associative. |
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* - The size of TLB0 must be a multiple of the number of ways, and |
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* the number of sets must be a power of two. |
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* - The size of TLB1 may not exceed 64 entries. |
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* - TLB0 supports 4 KiB pages. |
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* - The page sizes supported by TLB1 are as indicated by |
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* TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1) |
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* as returned by KVM_GET_SREGS. |
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* - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[] |
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* and tlb_ways[] must be zero. |
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* |
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* tlb_ways[n] = tlb_sizes[n] means the array is fully associative. |
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* |
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* KVM will adjust TLBnCFG based on the sizes configured here, |
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* though arrays greater than 2048 entries will have TLBnCFG[NENTRY] |
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* set to zero. |
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*/ |
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__u32 tlb_sizes[4]; |
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__u32 tlb_ways[4]; |
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__u32 reserved[8]; |
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}; |
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/* For KVM_PPC_GET_HTAB_FD */ |
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struct kvm_get_htab_fd { |
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__u64 flags; |
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__u64 start_index; |
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__u64 reserved[2]; |
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}; |
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/* Values for kvm_get_htab_fd.flags */ |
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#define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) |
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#define KVM_GET_HTAB_WRITE ((__u64)0x2) |
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/* |
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* Data read on the file descriptor is formatted as a series of |
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* records, each consisting of a header followed by a series of |
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* `n_valid' HPTEs (16 bytes each), which are all valid. Following |
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* those valid HPTEs there are `n_invalid' invalid HPTEs, which |
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* are not represented explicitly in the stream. The same format |
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* is used for writing. |
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*/ |
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struct kvm_get_htab_header { |
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__u32 index; |
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__u16 n_valid; |
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__u16 n_invalid; |
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}; |
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/* For KVM_PPC_CONFIGURE_V3_MMU */ |
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struct kvm_ppc_mmuv3_cfg { |
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__u64 flags; |
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__u64 process_table; /* second doubleword of partition table entry */ |
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}; |
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/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */ |
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#define KVM_PPC_MMUV3_RADIX 1 /* 1 = radix mode, 0 = HPT */ |
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#define KVM_PPC_MMUV3_GTSE 2 /* global translation shootdown enb. */ |
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/* For KVM_PPC_GET_RMMU_INFO */ |
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struct kvm_ppc_rmmu_info { |
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struct kvm_ppc_radix_geom { |
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__u8 page_shift; |
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__u8 level_bits[4]; |
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__u8 pad[3]; |
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} geometries[8]; |
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__u32 ap_encodings[8]; |
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}; |
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/* For KVM_PPC_GET_CPU_CHAR */ |
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struct kvm_ppc_cpu_char { |
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__u64 character; /* characteristics of the CPU */ |
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__u64 behaviour; /* recommended software behaviour */ |
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__u64 character_mask; /* valid bits in character */ |
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__u64 behaviour_mask; /* valid bits in behaviour */ |
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}; |
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/* |
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* Values for character and character_mask. |
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* These are identical to the values used by H_GET_CPU_CHARACTERISTICS. |
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*/ |
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#define KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31 (1ULL << 63) |
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#define KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED (1ULL << 62) |
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#define KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30 (1ULL << 61) |
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#define KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2 (1ULL << 60) |
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#define KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV (1ULL << 59) |
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#define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED (1ULL << 58) |
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#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF (1ULL << 57) |
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#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS (1ULL << 56) |
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#define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54) |
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#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY (1ULL << 63) |
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#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR (1ULL << 62) |
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#define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ULL << 61) |
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#define KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE (1ull << 58) |
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/* Per-vcpu XICS interrupt controller state */ |
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#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c) |
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#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */ |
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#define KVM_REG_PPC_ICP_CPPR_MASK 0xff |
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#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */ |
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#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff |
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#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */ |
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#define KVM_REG_PPC_ICP_MFRR_MASK 0xff |
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#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */ |
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#define KVM_REG_PPC_ICP_PPRI_MASK 0xff |
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#define KVM_REG_PPC_VP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x8d) |
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/* Device control API: PPC-specific devices */ |
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#define KVM_DEV_MPIC_GRP_MISC 1 |
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#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */ |
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#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */ |
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#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */ |
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/* One-Reg API: PPC-specific registers */ |
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#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1) |
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#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2) |
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#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3) |
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#define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4) |
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#define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5) |
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#define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6) |
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#define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7) |
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#define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8) |
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#define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9) |
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#define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa) |
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#define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb) |
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#define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc) |
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#define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd) |
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#define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe) |
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#define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf) |
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#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10) |
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#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11) |
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#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12) |
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#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13) |
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#define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14) |
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#define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15) |
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#define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16) |
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#define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17) |
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#define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18) |
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#define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19) |
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#define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a) |
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#define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b) |
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#define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c) |
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#define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d) |
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#define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e) |
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#define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f) |
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/* 32 floating-point registers */ |
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#define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20) |
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#define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n)) |
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#define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f) |
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/* 32 VMX/Altivec vector registers */ |
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#define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40) |
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#define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n)) |
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#define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f) |
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/* 32 double-width FP registers for VSX */ |
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/* High-order halves overlap with FP regs */ |
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#define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60) |
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#define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n)) |
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#define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f) |
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/* FP and vector status/control registers */ |
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#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80) |
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/* |
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* VSCR register is documented as a 32-bit register in the ISA, but it can |
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* only be accesses via a vector register. Expose VSCR as a 32-bit register |
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* even though the kernel represents it as a 128-bit vector. |
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*/ |
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#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81) |
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/* Virtual processor areas */ |
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/* For SLB & DTL, address in high (first) half, length in low half */ |
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#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82) |
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#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83) |
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#define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84) |
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#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85) |
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#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86) |
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/* Timer Status Register OR/CLEAR interface */ |
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#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87) |
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#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88) |
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#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89) |
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#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a) |
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/* Debugging: Special instruction for software breakpoint */ |
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#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b) |
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/* MMU registers */ |
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#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c) |
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#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d) |
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#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e) |
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#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f) |
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#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90) |
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#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91) |
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#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92) |
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/* |
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* TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using |
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* KVM_CAP_SW_TLB ioctl |
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*/ |
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#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93) |
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#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94) |
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#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95) |
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#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96) |
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#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97) |
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#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98) |
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#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99) |
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#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a) |
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#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b) |
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/* Timebase offset */ |
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#define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c) |
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/* POWER8 registers */ |
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#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d) |
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#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e) |
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#define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f) |
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#define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0) |
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#define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1) |
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#define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2) |
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#define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3) |
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#define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4) |
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#define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5) |
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#define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6) |
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#define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7) |
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#define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8) |
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#define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9) |
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#define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa) |
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#define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab) |
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#define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac) |
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#define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad) |
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#define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae) |
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#define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf) |
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#define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0) |
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#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1) |
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#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2) |
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#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3) |
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#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4) |
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#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5) |
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#define KVM_REG_PPC_LPCR_64 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5) |
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#define KVM_REG_PPC_PPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6) |
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/* Architecture compatibility level */ |
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#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7) |
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#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8) |
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#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9) |
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#define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba) |
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#define KVM_REG_PPC_DBSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb) |
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/* POWER9 registers */ |
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#define KVM_REG_PPC_TIDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc) |
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#define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd) |
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#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe) |
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#define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf) |
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#define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0) |
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/* POWER10 registers */ |
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#define KVM_REG_PPC_MMCR3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1) |
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#define KVM_REG_PPC_SIER2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2) |
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#define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) |
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#define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4) |
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#define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5) |
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/* Transactional Memory checkpointed state: |
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* This is all GPRs, all VSX regs and a subset of SPRs |
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*/ |
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#define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000) |
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/* TM GPRs */ |
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#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0) |
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#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n)) |
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#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f) |
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/* TM VSX */ |
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#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20) |
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#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n)) |
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#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f) |
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/* TM SPRS */ |
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#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60) |
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#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61) |
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#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62) |
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#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63) |
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#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64) |
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#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65) |
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#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66) |
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#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67) |
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#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68) |
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#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69) |
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#define KVM_REG_PPC_TM_XER (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a) |
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/* PPC64 eXternal Interrupt Controller Specification */ |
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#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */ |
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#define KVM_DEV_XICS_GRP_CTRL 2 |
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#define KVM_DEV_XICS_NR_SERVERS 1 |
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/* Layout of 64-bit source attribute values */ |
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#define KVM_XICS_DESTINATION_SHIFT 0 |
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#define KVM_XICS_DESTINATION_MASK 0xffffffffULL |
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#define KVM_XICS_PRIORITY_SHIFT 32 |
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#define KVM_XICS_PRIORITY_MASK 0xff |
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#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40) |
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#define KVM_XICS_MASKED (1ULL << 41) |
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#define KVM_XICS_PENDING (1ULL << 42) |
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#define KVM_XICS_PRESENTED (1ULL << 43) |
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#define KVM_XICS_QUEUED (1ULL << 44) |
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/* POWER9 XIVE Native Interrupt Controller */ |
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#define KVM_DEV_XIVE_GRP_CTRL 1 |
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#define KVM_DEV_XIVE_RESET 1 |
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#define KVM_DEV_XIVE_EQ_SYNC 2 |
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#define KVM_DEV_XIVE_NR_SERVERS 3 |
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#define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */ |
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#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */ |
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#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */ |
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#define KVM_DEV_XIVE_GRP_SOURCE_SYNC 5 /* 64-bit source identifier */ |
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/* Layout of 64-bit XIVE source attribute values */ |
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#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0) |
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#define KVM_XIVE_LEVEL_ASSERTED (1ULL << 1) |
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/* Layout of 64-bit XIVE source configuration attribute values */ |
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#define KVM_XIVE_SOURCE_PRIORITY_SHIFT 0 |
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#define KVM_XIVE_SOURCE_PRIORITY_MASK 0x7 |
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#define KVM_XIVE_SOURCE_SERVER_SHIFT 3 |
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#define KVM_XIVE_SOURCE_SERVER_MASK 0xfffffff8ULL |
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#define KVM_XIVE_SOURCE_MASKED_SHIFT 32 |
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#define KVM_XIVE_SOURCE_MASKED_MASK 0x100000000ULL |
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#define KVM_XIVE_SOURCE_EISN_SHIFT 33 |
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#define KVM_XIVE_SOURCE_EISN_MASK 0xfffffffe00000000ULL |
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/* Layout of 64-bit EQ identifier */ |
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#define KVM_XIVE_EQ_PRIORITY_SHIFT 0 |
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#define KVM_XIVE_EQ_PRIORITY_MASK 0x7 |
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#define KVM_XIVE_EQ_SERVER_SHIFT 3 |
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#define KVM_XIVE_EQ_SERVER_MASK 0xfffffff8ULL |
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/* Layout of EQ configuration values (64 bytes) */ |
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struct kvm_ppc_xive_eq { |
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__u32 flags; |
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__u32 qshift; |
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__u64 qaddr; |
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__u32 qtoggle; |
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__u32 qindex; |
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__u8 pad[40]; |
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}; |
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#define KVM_XIVE_EQ_ALWAYS_NOTIFY 0x00000001 |
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#define KVM_XIVE_TIMA_PAGE_OFFSET 0 |
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#define KVM_XIVE_ESB_PAGE_OFFSET 4 |
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#endif /* __LINUX_KVM_POWERPC_H */
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