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324 lines
8.7 KiB
324 lines
8.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/linkage.h> |
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#include <linux/interrupt.h> |
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#include <linux/spinlock.h> |
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#include <linux/smp.h> |
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#include <linux/mm.h> |
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#include <linux/kernel_stat.h> |
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#include <asm/errno.h> |
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#include <asm/signal.h> |
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#include <asm/time.h> |
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#include <asm/io.h> |
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#include <asm/sibyte/sb1250_regs.h> |
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#include <asm/sibyte/sb1250_int.h> |
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#include <asm/sibyte/sb1250_uart.h> |
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#include <asm/sibyte/sb1250_scd.h> |
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#include <asm/sibyte/sb1250.h> |
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/* |
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* These are the routines that handle all the low level interrupt stuff. |
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* Actions handled here are: initialization of the interrupt map, requesting of |
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* interrupt lines by handlers, dispatching if interrupts to handlers, probing |
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* for interrupt lines |
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*/ |
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#ifdef CONFIG_SIBYTE_HAS_LDT |
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extern unsigned long ldt_eoi_space; |
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#endif |
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/* Store the CPU id (not the logical number) */ |
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int sb1250_irq_owner[SB1250_NR_IRQS]; |
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static DEFINE_RAW_SPINLOCK(sb1250_imr_lock); |
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void sb1250_mask_irq(int cpu, int irq) |
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{ |
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unsigned long flags; |
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u64 cur_ints; |
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raw_spin_lock_irqsave(&sb1250_imr_lock, flags); |
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cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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cur_ints |= (((u64) 1) << irq); |
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____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
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} |
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void sb1250_unmask_irq(int cpu, int irq) |
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{ |
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unsigned long flags; |
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u64 cur_ints; |
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raw_spin_lock_irqsave(&sb1250_imr_lock, flags); |
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cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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cur_ints &= ~(((u64) 1) << irq); |
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____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
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} |
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#ifdef CONFIG_SMP |
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static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask, |
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bool force) |
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{ |
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int i = 0, old_cpu, cpu, int_on; |
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unsigned int irq = d->irq; |
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u64 cur_ints; |
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unsigned long flags; |
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i = cpumask_first_and(mask, cpu_online_mask); |
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/* Convert logical CPU to physical CPU */ |
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cpu = cpu_logical_map(i); |
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/* Protect against other affinity changers and IMR manipulation */ |
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raw_spin_lock_irqsave(&sb1250_imr_lock, flags); |
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/* Swizzle each CPU's IMR (but leave the IP selection alone) */ |
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old_cpu = sb1250_irq_owner[irq]; |
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cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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int_on = !(cur_ints & (((u64) 1) << irq)); |
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if (int_on) { |
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/* If it was on, mask it */ |
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cur_ints |= (((u64) 1) << irq); |
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____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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} |
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sb1250_irq_owner[irq] = cpu; |
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if (int_on) { |
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/* unmask for the new CPU */ |
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cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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cur_ints &= ~(((u64) 1) << irq); |
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____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
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R_IMR_INTERRUPT_MASK)); |
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} |
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raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
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return 0; |
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} |
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#endif |
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static void disable_sb1250_irq(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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sb1250_mask_irq(sb1250_irq_owner[irq], irq); |
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} |
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static void enable_sb1250_irq(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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sb1250_unmask_irq(sb1250_irq_owner[irq], irq); |
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} |
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static void ack_sb1250_irq(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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#ifdef CONFIG_SIBYTE_HAS_LDT |
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u64 pending; |
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/* |
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* If the interrupt was an HT interrupt, now is the time to |
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* clear it. NOTE: we assume the HT bridge was set up to |
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* deliver the interrupts to all CPUs (which makes affinity |
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* changing easier for us) |
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*/ |
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pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], |
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R_IMR_LDT_INTERRUPT))); |
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pending &= ((u64)1 << (irq)); |
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if (pending) { |
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int i; |
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for (i=0; i<NR_CPUS; i++) { |
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int cpu; |
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#ifdef CONFIG_SMP |
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cpu = cpu_logical_map(i); |
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#else |
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cpu = i; |
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#endif |
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/* |
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* Clear for all CPUs so an affinity switch |
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* doesn't find an old status |
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*/ |
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__raw_writeq(pending, |
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IOADDR(A_IMR_REGISTER(cpu, |
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R_IMR_LDT_INTERRUPT_CLR))); |
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} |
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/* |
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* Generate EOI. For Pass 1 parts, EOI is a nop. For |
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* Pass 2, the LDT world may be edge-triggered, but |
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* this EOI shouldn't hurt. If they are |
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* level-sensitive, the EOI is required. |
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*/ |
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*(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0; |
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} |
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#endif |
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sb1250_mask_irq(sb1250_irq_owner[irq], irq); |
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} |
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static struct irq_chip sb1250_irq_type = { |
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.name = "SB1250-IMR", |
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.irq_mask_ack = ack_sb1250_irq, |
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.irq_unmask = enable_sb1250_irq, |
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.irq_mask = disable_sb1250_irq, |
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#ifdef CONFIG_SMP |
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.irq_set_affinity = sb1250_set_affinity |
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#endif |
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}; |
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void __init init_sb1250_irqs(void) |
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{ |
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int i; |
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for (i = 0; i < SB1250_NR_IRQS; i++) { |
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irq_set_chip_and_handler(i, &sb1250_irq_type, |
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handle_level_irq); |
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sb1250_irq_owner[i] = 0; |
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} |
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} |
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/* |
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* arch_init_irq is called early in the boot sequence from init/main.c via |
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* init_IRQ. It is responsible for setting up the interrupt mapper and |
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* installing the handler that will be responsible for dispatching interrupts |
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* to the "right" place. |
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*/ |
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/* |
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* For now, map all interrupts to IP[2]. We could save |
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* some cycles by parceling out system interrupts to different |
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* IP lines, but keep it simple for bringup. We'll also direct |
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* all interrupts to a single CPU; we should probably route |
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* PCI and LDT to one cpu and everything else to the other |
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* to balance the load a bit. |
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* |
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* On the second cpu, everything is set to IP5, which is |
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* ignored, EXCEPT the mailbox interrupt. That one is |
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* set to IP[2] so it is handled. This is needed so we |
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* can do cross-cpu function calls, as required by SMP |
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*/ |
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#define IMR_IP2_VAL K_INT_MAP_I0 |
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#define IMR_IP3_VAL K_INT_MAP_I1 |
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#define IMR_IP4_VAL K_INT_MAP_I2 |
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#define IMR_IP5_VAL K_INT_MAP_I3 |
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#define IMR_IP6_VAL K_INT_MAP_I4 |
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void __init arch_init_irq(void) |
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{ |
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unsigned int i; |
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u64 tmp; |
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unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | |
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STATUSF_IP1 | STATUSF_IP0; |
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/* Default everything to IP2 */ |
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for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ |
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__raw_writeq(IMR_IP2_VAL, |
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IOADDR(A_IMR_REGISTER(0, |
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R_IMR_INTERRUPT_MAP_BASE) + |
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(i << 3))); |
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__raw_writeq(IMR_IP2_VAL, |
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IOADDR(A_IMR_REGISTER(1, |
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R_IMR_INTERRUPT_MAP_BASE) + |
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(i << 3))); |
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} |
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init_sb1250_irqs(); |
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/* |
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* Map the high 16 bits of the mailbox registers to IP[3], for |
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* inter-cpu messages |
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*/ |
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/* Was I1 */ |
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__raw_writeq(IMR_IP3_VAL, |
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IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + |
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(K_INT_MBOX_0 << 3))); |
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__raw_writeq(IMR_IP3_VAL, |
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IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + |
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(K_INT_MBOX_0 << 3))); |
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/* Clear the mailboxes. The firmware may leave them dirty */ |
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__raw_writeq(0xffffffffffffffffULL, |
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IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); |
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__raw_writeq(0xffffffffffffffffULL, |
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IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); |
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/* Mask everything except the mailbox registers for both cpus */ |
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tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); |
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__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); |
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__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); |
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/* |
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* Note that the timer interrupts are also mapped, but this is |
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* done in sb1250_time_init(). Also, the profiling driver |
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* does its own management of IP7. |
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*/ |
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/* Enable necessary IPs, disable the rest */ |
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change_c0_status(ST0_IM, imask); |
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} |
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extern void sb1250_mailbox_interrupt(void); |
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static inline void dispatch_ip2(void) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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unsigned long long mask; |
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/* |
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* Default...we've hit an IP[2] interrupt, which means we've got to |
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* check the 1250 interrupt registers to figure out what to do. Need |
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* to detect which CPU we're on, now that smp_affinity is supported. |
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*/ |
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mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu, |
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R_IMR_INTERRUPT_STATUS_BASE))); |
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if (mask) |
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do_IRQ(fls64(mask) - 1); |
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} |
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asmlinkage void plat_irq_dispatch(void) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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unsigned int pending; |
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/* |
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* What a pain. We have to be really careful saving the upper 32 bits |
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* of any * register across function calls if we don't want them |
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* trashed--since were running in -o32, the calling routing never saves |
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* the full 64 bits of a register across a function call. Being the |
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* interrupt handler, we're guaranteed that interrupts are disabled |
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* during this code so we don't have to worry about random interrupts |
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* blasting the high 32 bits. |
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*/ |
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pending = read_c0_cause() & read_c0_status() & ST0_IM; |
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if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ |
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do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
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else if (pending & CAUSEF_IP4) |
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do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */ |
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#ifdef CONFIG_SMP |
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else if (pending & CAUSEF_IP3) |
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sb1250_mailbox_interrupt(); |
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#endif |
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else if (pending & CAUSEF_IP2) |
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dispatch_ip2(); |
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else |
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spurious_interrupt(); |
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}
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