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467 lines
11 KiB
467 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Port on Texas Instruments TMS320C6x architecture |
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* |
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* Copyright (C) 2011 Texas Instruments Incorporated |
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* Author: Mark Salter <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/errno.h> |
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#include <linux/string.h> |
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#include <linux/ioport.h> |
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#include <linux/clkdev.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <asm/clock.h> |
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#include <asm/setup.h> |
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#include <asm/special_insns.h> |
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#include <asm/irq.h> |
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/* |
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* Common SoC clock support. |
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*/ |
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/* Default input for PLL1 */ |
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struct clk clkin1 = { |
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.name = "clkin1", |
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.node = LIST_HEAD_INIT(clkin1.node), |
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.children = LIST_HEAD_INIT(clkin1.children), |
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.childnode = LIST_HEAD_INIT(clkin1.childnode), |
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}; |
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struct pll_data c6x_soc_pll1 = { |
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.num = 1, |
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.sysclks = { |
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{ |
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.name = "pll1", |
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.parent = &clkin1, |
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.pll_data = &c6x_soc_pll1, |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk1", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk2", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk3", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk4", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk5", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk6", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk7", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk8", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk9", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk10", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk11", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk12", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk13", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk14", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk15", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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{ |
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.name = "pll1_sysclk16", |
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.parent = &c6x_soc_pll1.sysclks[0], |
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.flags = CLK_PLL, |
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}, |
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}, |
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}; |
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/* CPU core clock */ |
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struct clk c6x_core_clk = { |
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.name = "core", |
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}; |
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/* miscellaneous IO clocks */ |
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struct clk c6x_i2c_clk = { |
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.name = "i2c", |
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}; |
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struct clk c6x_watchdog_clk = { |
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.name = "watchdog", |
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}; |
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struct clk c6x_mcbsp1_clk = { |
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.name = "mcbsp1", |
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}; |
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struct clk c6x_mcbsp2_clk = { |
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.name = "mcbsp2", |
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}; |
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struct clk c6x_mdio_clk = { |
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.name = "mdio", |
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}; |
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#ifdef CONFIG_SOC_TMS320C6455 |
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static struct clk_lookup c6455_clks[] = { |
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CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]), |
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CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]), |
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CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]), |
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CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]), |
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CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]), |
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CLK(NULL, "core", &c6x_core_clk), |
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CLK("i2c_davinci.1", NULL, &c6x_i2c_clk), |
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CLK("watchdog", NULL, &c6x_watchdog_clk), |
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CLK("2c81800.mdio", NULL, &c6x_mdio_clk), |
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CLK("", NULL, NULL) |
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}; |
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static void __init c6455_setup_clocks(struct device_node *node) |
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{ |
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struct pll_data *pll = &c6x_soc_pll1; |
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struct clk *sysclks = pll->sysclks; |
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pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; |
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sysclks[2].flags |= FIXED_DIV_PLL; |
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sysclks[2].div = 3; |
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sysclks[3].flags |= FIXED_DIV_PLL; |
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sysclks[3].div = 6; |
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sysclks[4].div = PLLDIV4; |
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sysclks[5].div = PLLDIV5; |
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c6x_core_clk.parent = &sysclks[0]; |
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c6x_i2c_clk.parent = &sysclks[3]; |
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c6x_watchdog_clk.parent = &sysclks[3]; |
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c6x_mdio_clk.parent = &sysclks[3]; |
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c6x_clks_init(c6455_clks); |
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} |
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#endif /* CONFIG_SOC_TMS320C6455 */ |
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#ifdef CONFIG_SOC_TMS320C6457 |
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static struct clk_lookup c6457_clks[] = { |
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CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]), |
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CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]), |
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CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]), |
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CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]), |
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CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]), |
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CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]), |
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CLK(NULL, "core", &c6x_core_clk), |
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CLK("i2c_davinci.1", NULL, &c6x_i2c_clk), |
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CLK("watchdog", NULL, &c6x_watchdog_clk), |
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CLK("2c81800.mdio", NULL, &c6x_mdio_clk), |
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CLK("", NULL, NULL) |
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}; |
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static void __init c6457_setup_clocks(struct device_node *node) |
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{ |
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struct pll_data *pll = &c6x_soc_pll1; |
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struct clk *sysclks = pll->sysclks; |
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pll->flags = PLL_HAS_MUL | PLL_HAS_POST; |
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sysclks[1].flags |= FIXED_DIV_PLL; |
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sysclks[1].div = 1; |
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sysclks[2].flags |= FIXED_DIV_PLL; |
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sysclks[2].div = 3; |
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sysclks[3].flags |= FIXED_DIV_PLL; |
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sysclks[3].div = 6; |
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sysclks[4].div = PLLDIV4; |
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sysclks[5].div = PLLDIV5; |
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c6x_core_clk.parent = &sysclks[1]; |
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c6x_i2c_clk.parent = &sysclks[3]; |
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c6x_watchdog_clk.parent = &sysclks[5]; |
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c6x_mdio_clk.parent = &sysclks[5]; |
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c6x_clks_init(c6457_clks); |
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} |
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#endif /* CONFIG_SOC_TMS320C6455 */ |
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#ifdef CONFIG_SOC_TMS320C6472 |
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static struct clk_lookup c6472_clks[] = { |
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CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]), |
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CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]), |
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CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]), |
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CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]), |
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CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]), |
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CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]), |
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CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]), |
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CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]), |
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CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]), |
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CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]), |
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CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]), |
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CLK(NULL, "core", &c6x_core_clk), |
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CLK("i2c_davinci.1", NULL, &c6x_i2c_clk), |
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CLK("watchdog", NULL, &c6x_watchdog_clk), |
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CLK("2c81800.mdio", NULL, &c6x_mdio_clk), |
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CLK("", NULL, NULL) |
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}; |
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/* assumptions used for delay loop calculations */ |
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#define MIN_CLKIN1_KHz 15625 |
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#define MAX_CORE_KHz 700000 |
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#define MIN_PLLOUT_KHz MIN_CLKIN1_KHz |
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static void __init c6472_setup_clocks(struct device_node *node) |
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{ |
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struct pll_data *pll = &c6x_soc_pll1; |
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struct clk *sysclks = pll->sysclks; |
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int i; |
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pll->flags = PLL_HAS_MUL; |
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for (i = 1; i <= 6; i++) { |
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sysclks[i].flags |= FIXED_DIV_PLL; |
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sysclks[i].div = 1; |
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} |
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sysclks[7].flags |= FIXED_DIV_PLL; |
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sysclks[7].div = 3; |
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sysclks[8].flags |= FIXED_DIV_PLL; |
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sysclks[8].div = 6; |
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sysclks[9].flags |= FIXED_DIV_PLL; |
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sysclks[9].div = 2; |
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sysclks[10].div = PLLDIV10; |
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c6x_core_clk.parent = &sysclks[get_coreid() + 1]; |
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c6x_i2c_clk.parent = &sysclks[8]; |
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c6x_watchdog_clk.parent = &sysclks[8]; |
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c6x_mdio_clk.parent = &sysclks[5]; |
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c6x_clks_init(c6472_clks); |
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} |
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#endif /* CONFIG_SOC_TMS320C6472 */ |
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#ifdef CONFIG_SOC_TMS320C6474 |
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static struct clk_lookup c6474_clks[] = { |
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CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]), |
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CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]), |
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CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]), |
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CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]), |
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CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]), |
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CLK(NULL, "pll1_sysclk12", &c6x_soc_pll1.sysclks[12]), |
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CLK(NULL, "pll1_sysclk13", &c6x_soc_pll1.sysclks[13]), |
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CLK(NULL, "core", &c6x_core_clk), |
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CLK("i2c_davinci.1", NULL, &c6x_i2c_clk), |
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CLK("mcbsp.1", NULL, &c6x_mcbsp1_clk), |
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CLK("mcbsp.2", NULL, &c6x_mcbsp2_clk), |
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CLK("watchdog", NULL, &c6x_watchdog_clk), |
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CLK("2c81800.mdio", NULL, &c6x_mdio_clk), |
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CLK("", NULL, NULL) |
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}; |
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static void __init c6474_setup_clocks(struct device_node *node) |
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{ |
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struct pll_data *pll = &c6x_soc_pll1; |
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struct clk *sysclks = pll->sysclks; |
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pll->flags = PLL_HAS_MUL; |
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sysclks[7].flags |= FIXED_DIV_PLL; |
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sysclks[7].div = 1; |
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sysclks[9].flags |= FIXED_DIV_PLL; |
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sysclks[9].div = 3; |
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sysclks[10].flags |= FIXED_DIV_PLL; |
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sysclks[10].div = 6; |
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sysclks[11].div = PLLDIV11; |
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sysclks[12].flags |= FIXED_DIV_PLL; |
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sysclks[12].div = 2; |
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sysclks[13].div = PLLDIV13; |
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c6x_core_clk.parent = &sysclks[7]; |
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c6x_i2c_clk.parent = &sysclks[10]; |
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c6x_watchdog_clk.parent = &sysclks[10]; |
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c6x_mcbsp1_clk.parent = &sysclks[10]; |
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c6x_mcbsp2_clk.parent = &sysclks[10]; |
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c6x_clks_init(c6474_clks); |
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} |
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#endif /* CONFIG_SOC_TMS320C6474 */ |
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#ifdef CONFIG_SOC_TMS320C6678 |
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static struct clk_lookup c6678_clks[] = { |
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CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]), |
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CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]), |
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CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]), |
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CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]), |
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CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]), |
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CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]), |
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CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]), |
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CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]), |
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CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]), |
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CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]), |
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CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]), |
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CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]), |
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CLK(NULL, "core", &c6x_core_clk), |
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CLK("", NULL, NULL) |
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}; |
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static void __init c6678_setup_clocks(struct device_node *node) |
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{ |
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struct pll_data *pll = &c6x_soc_pll1; |
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struct clk *sysclks = pll->sysclks; |
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pll->flags = PLL_HAS_MUL; |
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sysclks[1].flags |= FIXED_DIV_PLL; |
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sysclks[1].div = 1; |
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sysclks[2].div = PLLDIV2; |
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sysclks[3].flags |= FIXED_DIV_PLL; |
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sysclks[3].div = 2; |
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sysclks[4].flags |= FIXED_DIV_PLL; |
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sysclks[4].div = 3; |
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sysclks[5].div = PLLDIV5; |
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sysclks[6].flags |= FIXED_DIV_PLL; |
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sysclks[6].div = 64; |
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sysclks[7].flags |= FIXED_DIV_PLL; |
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sysclks[7].div = 6; |
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sysclks[8].div = PLLDIV8; |
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sysclks[9].flags |= FIXED_DIV_PLL; |
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sysclks[9].div = 12; |
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sysclks[10].flags |= FIXED_DIV_PLL; |
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sysclks[10].div = 3; |
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sysclks[11].flags |= FIXED_DIV_PLL; |
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sysclks[11].div = 6; |
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c6x_core_clk.parent = &sysclks[0]; |
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c6x_i2c_clk.parent = &sysclks[7]; |
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c6x_clks_init(c6678_clks); |
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} |
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#endif /* CONFIG_SOC_TMS320C6678 */ |
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static struct of_device_id c6x_clkc_match[] __initdata = { |
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#ifdef CONFIG_SOC_TMS320C6455 |
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{ .compatible = "ti,c6455-pll", .data = c6455_setup_clocks }, |
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#endif |
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#ifdef CONFIG_SOC_TMS320C6457 |
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{ .compatible = "ti,c6457-pll", .data = c6457_setup_clocks }, |
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#endif |
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#ifdef CONFIG_SOC_TMS320C6472 |
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{ .compatible = "ti,c6472-pll", .data = c6472_setup_clocks }, |
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#endif |
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#ifdef CONFIG_SOC_TMS320C6474 |
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{ .compatible = "ti,c6474-pll", .data = c6474_setup_clocks }, |
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#endif |
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#ifdef CONFIG_SOC_TMS320C6678 |
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{ .compatible = "ti,c6678-pll", .data = c6678_setup_clocks }, |
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#endif |
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{ .compatible = "ti,c64x+pll" }, |
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{} |
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}; |
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void __init c64x_setup_clocks(void) |
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{ |
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void (*__setup_clocks)(struct device_node *np); |
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struct pll_data *pll = &c6x_soc_pll1; |
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struct device_node *node; |
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const struct of_device_id *id; |
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int err; |
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u32 val; |
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node = of_find_matching_node(NULL, c6x_clkc_match); |
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if (!node) |
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return; |
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pll->base = of_iomap(node, 0); |
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if (!pll->base) |
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goto out; |
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err = of_property_read_u32(node, "clock-frequency", &val); |
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if (err || val == 0) { |
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pr_err("%pOF: no clock-frequency found! Using %dMHz\n", |
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node, (int)val / 1000000); |
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val = 25000000; |
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} |
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clkin1.rate = val; |
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err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val); |
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if (err) |
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val = 5000; |
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pll->bypass_delay = val; |
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err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val); |
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if (err) |
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val = 30000; |
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pll->reset_delay = val; |
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err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val); |
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if (err) |
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val = 30000; |
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pll->lock_delay = val; |
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/* id->data is a pointer to SoC-specific setup */ |
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id = of_match_node(c6x_clkc_match, node); |
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if (id && id->data) { |
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__setup_clocks = id->data; |
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__setup_clocks(node); |
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} |
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out: |
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of_node_put(node); |
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}
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