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344 lines
7.9 KiB
344 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Support for C64x+ Megamodule Interrupt Controller |
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* |
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* Copyright (C) 2010, 2011 Texas Instruments Incorporated |
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* Contributed by: Mark Salter <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <asm/soc.h> |
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#include <asm/megamod-pic.h> |
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#define NR_COMBINERS 4 |
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#define NR_MUX_OUTPUTS 12 |
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#define IRQ_UNMAPPED 0xffff |
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/* |
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* Megamodule Interrupt Controller register layout |
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*/ |
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struct megamod_regs { |
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u32 evtflag[8]; |
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u32 evtset[8]; |
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u32 evtclr[8]; |
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u32 reserved0[8]; |
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u32 evtmask[8]; |
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u32 mevtflag[8]; |
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u32 expmask[8]; |
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u32 mexpflag[8]; |
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u32 intmux_unused; |
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u32 intmux[7]; |
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u32 reserved1[8]; |
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u32 aegmux[2]; |
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u32 reserved2[14]; |
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u32 intxstat; |
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u32 intxclr; |
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u32 intdmask; |
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u32 reserved3[13]; |
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u32 evtasrt; |
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}; |
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struct megamod_pic { |
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struct irq_domain *irqhost; |
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struct megamod_regs __iomem *regs; |
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raw_spinlock_t lock; |
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/* hw mux mapping */ |
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unsigned int output_to_irq[NR_MUX_OUTPUTS]; |
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}; |
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static struct megamod_pic *mm_pic; |
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struct megamod_cascade_data { |
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struct megamod_pic *pic; |
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int index; |
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}; |
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static struct megamod_cascade_data cascade_data[NR_COMBINERS]; |
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static void mask_megamod(struct irq_data *data) |
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{ |
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struct megamod_pic *pic = irq_data_get_irq_chip_data(data); |
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irq_hw_number_t src = irqd_to_hwirq(data); |
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u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; |
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raw_spin_lock(&pic->lock); |
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soc_writel(soc_readl(evtmask) | (1 << (src & 31)), evtmask); |
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raw_spin_unlock(&pic->lock); |
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} |
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static void unmask_megamod(struct irq_data *data) |
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{ |
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struct megamod_pic *pic = irq_data_get_irq_chip_data(data); |
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irq_hw_number_t src = irqd_to_hwirq(data); |
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u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; |
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raw_spin_lock(&pic->lock); |
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soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask); |
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raw_spin_unlock(&pic->lock); |
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} |
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static struct irq_chip megamod_chip = { |
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.name = "megamod", |
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.irq_mask = mask_megamod, |
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.irq_unmask = unmask_megamod, |
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}; |
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static void megamod_irq_cascade(struct irq_desc *desc) |
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{ |
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struct megamod_cascade_data *cascade; |
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struct megamod_pic *pic; |
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unsigned int irq; |
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u32 events; |
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int n, idx; |
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cascade = irq_desc_get_handler_data(desc); |
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pic = cascade->pic; |
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idx = cascade->index; |
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while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) { |
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n = __ffs(events); |
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irq = irq_linear_revmap(pic->irqhost, idx * 32 + n); |
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soc_writel(1 << n, &pic->regs->evtclr[idx]); |
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generic_handle_irq(irq); |
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} |
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} |
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static int megamod_map(struct irq_domain *h, unsigned int virq, |
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irq_hw_number_t hw) |
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{ |
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struct megamod_pic *pic = h->host_data; |
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int i; |
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/* We shouldn't see a hwirq which is muxed to core controller */ |
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for (i = 0; i < NR_MUX_OUTPUTS; i++) |
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if (pic->output_to_irq[i] == hw) |
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return -1; |
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irq_set_chip_data(virq, pic); |
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irq_set_chip_and_handler(virq, &megamod_chip, handle_level_irq); |
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/* Set default irq type */ |
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irq_set_irq_type(virq, IRQ_TYPE_NONE); |
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return 0; |
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} |
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static const struct irq_domain_ops megamod_domain_ops = { |
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.map = megamod_map, |
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.xlate = irq_domain_xlate_onecell, |
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}; |
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static void __init set_megamod_mux(struct megamod_pic *pic, int src, int output) |
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{ |
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int index, offset; |
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u32 val; |
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if (src < 0 || src >= (NR_COMBINERS * 32)) { |
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pic->output_to_irq[output] = IRQ_UNMAPPED; |
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return; |
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} |
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/* four mappings per mux register */ |
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index = output / 4; |
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offset = (output & 3) * 8; |
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val = soc_readl(&pic->regs->intmux[index]); |
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val &= ~(0xff << offset); |
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val |= src << offset; |
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soc_writel(val, &pic->regs->intmux[index]); |
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} |
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/* |
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* Parse the MUX mapping, if one exists. |
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* |
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* The MUX map is an array of up to 12 cells; one for each usable core priority |
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* interrupt. The value of a given cell is the megamodule interrupt source |
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* which is to me MUXed to the output corresponding to the cell position |
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* withing the array. The first cell in the array corresponds to priority |
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* 4 and the last (12th) cell corresponds to priority 15. The allowed |
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* values are 4 - ((NR_COMBINERS * 32) - 1). Note that the combined interrupt |
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* sources (0 - 3) are not allowed to be mapped through this property. They |
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* are handled through the "interrupts" property. This allows us to use a |
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* value of zero as a "do not map" placeholder. |
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*/ |
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static void __init parse_priority_map(struct megamod_pic *pic, |
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int *mapping, int size) |
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{ |
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struct device_node *np = irq_domain_get_of_node(pic->irqhost); |
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const __be32 *map; |
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int i, maplen; |
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u32 val; |
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map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen); |
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if (map) { |
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maplen /= 4; |
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if (maplen > size) |
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maplen = size; |
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for (i = 0; i < maplen; i++) { |
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val = be32_to_cpup(map); |
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if (val && val >= 4) |
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mapping[i] = val; |
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++map; |
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} |
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} |
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} |
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static struct megamod_pic * __init init_megamod_pic(struct device_node *np) |
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{ |
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struct megamod_pic *pic; |
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int i, irq; |
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int mapping[NR_MUX_OUTPUTS]; |
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pr_info("Initializing C64x+ Megamodule PIC\n"); |
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pic = kzalloc(sizeof(struct megamod_pic), GFP_KERNEL); |
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if (!pic) { |
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pr_err("%pOF: Could not alloc PIC structure.\n", np); |
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return NULL; |
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} |
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pic->irqhost = irq_domain_add_linear(np, NR_COMBINERS * 32, |
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&megamod_domain_ops, pic); |
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if (!pic->irqhost) { |
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pr_err("%pOF: Could not alloc host.\n", np); |
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goto error_free; |
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} |
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pic->irqhost->host_data = pic; |
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raw_spin_lock_init(&pic->lock); |
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pic->regs = of_iomap(np, 0); |
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if (!pic->regs) { |
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pr_err("%pOF: Could not map registers.\n", np); |
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goto error_free; |
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} |
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/* Initialize MUX map */ |
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for (i = 0; i < ARRAY_SIZE(mapping); i++) |
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mapping[i] = IRQ_UNMAPPED; |
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parse_priority_map(pic, mapping, ARRAY_SIZE(mapping)); |
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/* |
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* We can have up to 12 interrupts cascading to the core controller. |
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* These cascades can be from the combined interrupt sources or for |
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* individual interrupt sources. The "interrupts" property only |
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* deals with the cascaded combined interrupts. The individual |
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* interrupts muxed to the core controller use the core controller |
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* as their interrupt parent. |
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*/ |
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for (i = 0; i < NR_COMBINERS; i++) { |
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struct irq_data *irq_data; |
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irq_hw_number_t hwirq; |
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irq = irq_of_parse_and_map(np, i); |
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if (irq == NO_IRQ) |
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continue; |
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irq_data = irq_get_irq_data(irq); |
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if (!irq_data) { |
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pr_err("%pOF: combiner-%d no irq_data for virq %d!\n", |
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np, i, irq); |
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continue; |
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} |
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hwirq = irq_data->hwirq; |
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/* |
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* Check that device tree provided something in the range |
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* of the core priority interrupts (4 - 15). |
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*/ |
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if (hwirq < 4 || hwirq >= NR_PRIORITY_IRQS) { |
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pr_err("%pOF: combiner-%d core irq %ld out of range!\n", |
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np, i, hwirq); |
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continue; |
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} |
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/* record the mapping */ |
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mapping[hwirq - 4] = i; |
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pr_debug("%pOF: combiner-%d cascading to hwirq %ld\n", |
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np, i, hwirq); |
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cascade_data[i].pic = pic; |
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cascade_data[i].index = i; |
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/* mask and clear all events in combiner */ |
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soc_writel(~0, &pic->regs->evtmask[i]); |
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soc_writel(~0, &pic->regs->evtclr[i]); |
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irq_set_chained_handler_and_data(irq, megamod_irq_cascade, |
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&cascade_data[i]); |
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} |
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/* Finally, set up the MUX registers */ |
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for (i = 0; i < NR_MUX_OUTPUTS; i++) { |
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if (mapping[i] != IRQ_UNMAPPED) { |
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pr_debug("%pOF: setting mux %d to priority %d\n", |
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np, mapping[i], i + 4); |
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set_megamod_mux(pic, mapping[i], i); |
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} |
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} |
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return pic; |
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error_free: |
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kfree(pic); |
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return NULL; |
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} |
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/* |
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* Return next active event after ACK'ing it. |
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* Return -1 if no events active. |
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*/ |
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static int get_exception(void) |
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{ |
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int i, bit; |
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u32 mask; |
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for (i = 0; i < NR_COMBINERS; i++) { |
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mask = soc_readl(&mm_pic->regs->mexpflag[i]); |
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if (mask) { |
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bit = __ffs(mask); |
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soc_writel(1 << bit, &mm_pic->regs->evtclr[i]); |
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return (i * 32) + bit; |
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} |
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} |
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return -1; |
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} |
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static void assert_event(unsigned int val) |
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{ |
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soc_writel(val, &mm_pic->regs->evtasrt); |
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} |
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void __init megamod_pic_init(void) |
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{ |
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struct device_node *np; |
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np = of_find_compatible_node(NULL, NULL, "ti,c64x+megamod-pic"); |
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if (!np) |
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return; |
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mm_pic = init_megamod_pic(np); |
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of_node_put(np); |
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soc_ops.get_exception = get_exception; |
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soc_ops.assert_event = assert_event; |
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return; |
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}
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