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224 lines
5.6 KiB
224 lines
5.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2012,2013 - ARM Ltd |
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* Author: Marc Zyngier <[email protected]> |
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* |
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* Derived from arch/arm/kvm/emulate.c: |
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University |
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* Author: Christoffer Dall <[email protected]> |
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*/ |
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#include <linux/mm.h> |
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#include <linux/kvm_host.h> |
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#include <asm/kvm_emulate.h> |
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#include <asm/ptrace.h> |
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#define VCPU_NR_MODES 6 |
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#define REG_OFFSET(_reg) \ |
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(offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long)) |
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#define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R)) |
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static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][16] = { |
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/* USR Registers */ |
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{ |
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), |
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), |
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), |
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), |
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USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14), |
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REG_OFFSET(pc) |
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}, |
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/* FIQ Registers */ |
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{ |
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), |
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), |
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), |
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REG_OFFSET(compat_r8_fiq), /* r8 */ |
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REG_OFFSET(compat_r9_fiq), /* r9 */ |
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REG_OFFSET(compat_r10_fiq), /* r10 */ |
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REG_OFFSET(compat_r11_fiq), /* r11 */ |
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REG_OFFSET(compat_r12_fiq), /* r12 */ |
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REG_OFFSET(compat_sp_fiq), /* r13 */ |
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REG_OFFSET(compat_lr_fiq), /* r14 */ |
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REG_OFFSET(pc) |
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}, |
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/* IRQ Registers */ |
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{ |
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), |
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), |
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), |
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), |
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USR_REG_OFFSET(12), |
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REG_OFFSET(compat_sp_irq), /* r13 */ |
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REG_OFFSET(compat_lr_irq), /* r14 */ |
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REG_OFFSET(pc) |
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}, |
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/* SVC Registers */ |
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{ |
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), |
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), |
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), |
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), |
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USR_REG_OFFSET(12), |
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REG_OFFSET(compat_sp_svc), /* r13 */ |
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REG_OFFSET(compat_lr_svc), /* r14 */ |
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REG_OFFSET(pc) |
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}, |
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/* ABT Registers */ |
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{ |
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), |
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), |
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), |
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), |
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USR_REG_OFFSET(12), |
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REG_OFFSET(compat_sp_abt), /* r13 */ |
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REG_OFFSET(compat_lr_abt), /* r14 */ |
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REG_OFFSET(pc) |
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}, |
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/* UND Registers */ |
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{ |
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2), |
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5), |
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8), |
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11), |
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USR_REG_OFFSET(12), |
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REG_OFFSET(compat_sp_und), /* r13 */ |
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REG_OFFSET(compat_lr_und), /* r14 */ |
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REG_OFFSET(pc) |
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}, |
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}; |
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/* |
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* Return a pointer to the register number valid in the current mode of |
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* the virtual CPU. |
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*/ |
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num) |
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{ |
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unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.regs; |
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unsigned long mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; |
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switch (mode) { |
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case PSR_AA32_MODE_USR ... PSR_AA32_MODE_SVC: |
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mode &= ~PSR_MODE32_BIT; /* 0 ... 3 */ |
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break; |
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case PSR_AA32_MODE_ABT: |
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mode = 4; |
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break; |
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case PSR_AA32_MODE_UND: |
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mode = 5; |
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break; |
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case PSR_AA32_MODE_SYS: |
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mode = 0; /* SYS maps to USR */ |
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break; |
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default: |
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BUG(); |
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} |
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return reg_array + vcpu_reg_offsets[mode][reg_num]; |
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} |
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/* |
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* Return the SPSR for the current mode of the virtual CPU. |
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*/ |
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static int vcpu_spsr32_mode(const struct kvm_vcpu *vcpu) |
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{ |
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unsigned long mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; |
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switch (mode) { |
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case PSR_AA32_MODE_SVC: return KVM_SPSR_SVC; |
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case PSR_AA32_MODE_ABT: return KVM_SPSR_ABT; |
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case PSR_AA32_MODE_UND: return KVM_SPSR_UND; |
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case PSR_AA32_MODE_IRQ: return KVM_SPSR_IRQ; |
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case PSR_AA32_MODE_FIQ: return KVM_SPSR_FIQ; |
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default: BUG(); |
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} |
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} |
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unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu) |
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{ |
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int spsr_idx = vcpu_spsr32_mode(vcpu); |
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if (!vcpu->arch.sysregs_loaded_on_cpu) { |
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switch (spsr_idx) { |
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case KVM_SPSR_SVC: |
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return __vcpu_sys_reg(vcpu, SPSR_EL1); |
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case KVM_SPSR_ABT: |
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return vcpu->arch.ctxt.spsr_abt; |
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case KVM_SPSR_UND: |
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return vcpu->arch.ctxt.spsr_und; |
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case KVM_SPSR_IRQ: |
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return vcpu->arch.ctxt.spsr_irq; |
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case KVM_SPSR_FIQ: |
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return vcpu->arch.ctxt.spsr_fiq; |
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} |
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} |
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switch (spsr_idx) { |
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case KVM_SPSR_SVC: |
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return read_sysreg_el1(SYS_SPSR); |
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case KVM_SPSR_ABT: |
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return read_sysreg(spsr_abt); |
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case KVM_SPSR_UND: |
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return read_sysreg(spsr_und); |
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case KVM_SPSR_IRQ: |
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return read_sysreg(spsr_irq); |
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case KVM_SPSR_FIQ: |
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return read_sysreg(spsr_fiq); |
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default: |
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BUG(); |
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} |
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} |
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void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v) |
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{ |
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int spsr_idx = vcpu_spsr32_mode(vcpu); |
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if (!vcpu->arch.sysregs_loaded_on_cpu) { |
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switch (spsr_idx) { |
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case KVM_SPSR_SVC: |
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__vcpu_sys_reg(vcpu, SPSR_EL1) = v; |
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break; |
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case KVM_SPSR_ABT: |
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vcpu->arch.ctxt.spsr_abt = v; |
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break; |
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case KVM_SPSR_UND: |
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vcpu->arch.ctxt.spsr_und = v; |
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break; |
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case KVM_SPSR_IRQ: |
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vcpu->arch.ctxt.spsr_irq = v; |
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break; |
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case KVM_SPSR_FIQ: |
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vcpu->arch.ctxt.spsr_fiq = v; |
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break; |
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} |
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return; |
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} |
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switch (spsr_idx) { |
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case KVM_SPSR_SVC: |
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write_sysreg_el1(v, SYS_SPSR); |
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break; |
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case KVM_SPSR_ABT: |
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write_sysreg(v, spsr_abt); |
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break; |
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case KVM_SPSR_UND: |
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write_sysreg(v, spsr_und); |
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break; |
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case KVM_SPSR_IRQ: |
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write_sysreg(v, spsr_irq); |
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break; |
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case KVM_SPSR_FIQ: |
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write_sysreg(v, spsr_fiq); |
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break; |
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} |
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}
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