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377 lines
11 KiB
377 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2014-2017 Linaro Ltd. <[email protected]> |
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*/ |
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#include <linux/elf.h> |
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#include <linux/ftrace.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/sort.h> |
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static struct plt_entry __get_adrp_add_pair(u64 dst, u64 pc, |
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enum aarch64_insn_register reg) |
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{ |
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u32 adrp, add; |
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adrp = aarch64_insn_gen_adr(pc, dst, reg, AARCH64_INSN_ADR_TYPE_ADRP); |
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add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K, |
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AARCH64_INSN_VARIANT_64BIT, |
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AARCH64_INSN_ADSB_ADD); |
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return (struct plt_entry){ cpu_to_le32(adrp), cpu_to_le32(add) }; |
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} |
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struct plt_entry get_plt_entry(u64 dst, void *pc) |
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{ |
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struct plt_entry plt; |
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static u32 br; |
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if (!br) |
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br = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_16, |
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AARCH64_INSN_BRANCH_NOLINK); |
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plt = __get_adrp_add_pair(dst, (u64)pc, AARCH64_INSN_REG_16); |
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plt.br = cpu_to_le32(br); |
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return plt; |
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} |
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bool plt_entries_equal(const struct plt_entry *a, const struct plt_entry *b) |
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{ |
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u64 p, q; |
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/* |
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* Check whether both entries refer to the same target: |
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* do the cheapest checks first. |
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* If the 'add' or 'br' opcodes are different, then the target |
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* cannot be the same. |
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*/ |
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if (a->add != b->add || a->br != b->br) |
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return false; |
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p = ALIGN_DOWN((u64)a, SZ_4K); |
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q = ALIGN_DOWN((u64)b, SZ_4K); |
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/* |
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* If the 'adrp' opcodes are the same then we just need to check |
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* that they refer to the same 4k region. |
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*/ |
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if (a->adrp == b->adrp && p == q) |
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return true; |
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return (p + aarch64_insn_adrp_get_offset(le32_to_cpu(a->adrp))) == |
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(q + aarch64_insn_adrp_get_offset(le32_to_cpu(b->adrp))); |
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} |
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static bool in_init(const struct module *mod, void *loc) |
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{ |
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return (u64)loc - (u64)mod->init_layout.base < mod->init_layout.size; |
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} |
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u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs, |
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void *loc, const Elf64_Rela *rela, |
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Elf64_Sym *sym) |
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{ |
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struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core : |
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&mod->arch.init; |
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struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr; |
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int i = pltsec->plt_num_entries; |
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int j = i - 1; |
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u64 val = sym->st_value + rela->r_addend; |
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if (is_forbidden_offset_for_adrp(&plt[i].adrp)) |
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i++; |
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plt[i] = get_plt_entry(val, &plt[i]); |
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/* |
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* Check if the entry we just created is a duplicate. Given that the |
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* relocations are sorted, this will be the last entry we allocated. |
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* (if one exists). |
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*/ |
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if (j >= 0 && plt_entries_equal(plt + i, plt + j)) |
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return (u64)&plt[j]; |
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pltsec->plt_num_entries += i - j; |
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if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries)) |
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return 0; |
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return (u64)&plt[i]; |
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} |
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#ifdef CONFIG_ARM64_ERRATUM_843419 |
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u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs, |
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void *loc, u64 val) |
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{ |
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struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core : |
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&mod->arch.init; |
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struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr; |
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int i = pltsec->plt_num_entries++; |
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u32 br; |
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int rd; |
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if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries)) |
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return 0; |
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if (is_forbidden_offset_for_adrp(&plt[i].adrp)) |
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i = pltsec->plt_num_entries++; |
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/* get the destination register of the ADRP instruction */ |
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rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, |
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le32_to_cpup((__le32 *)loc)); |
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br = aarch64_insn_gen_branch_imm((u64)&plt[i].br, (u64)loc + 4, |
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AARCH64_INSN_BRANCH_NOLINK); |
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plt[i] = __get_adrp_add_pair(val, (u64)&plt[i], rd); |
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plt[i].br = cpu_to_le32(br); |
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return (u64)&plt[i]; |
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} |
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#endif |
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#define cmp_3way(a, b) ((a) < (b) ? -1 : (a) > (b)) |
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static int cmp_rela(const void *a, const void *b) |
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{ |
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const Elf64_Rela *x = a, *y = b; |
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int i; |
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/* sort by type, symbol index and addend */ |
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i = cmp_3way(ELF64_R_TYPE(x->r_info), ELF64_R_TYPE(y->r_info)); |
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if (i == 0) |
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i = cmp_3way(ELF64_R_SYM(x->r_info), ELF64_R_SYM(y->r_info)); |
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if (i == 0) |
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i = cmp_3way(x->r_addend, y->r_addend); |
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return i; |
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} |
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static bool duplicate_rel(const Elf64_Rela *rela, int num) |
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{ |
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/* |
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* Entries are sorted by type, symbol index and addend. That means |
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* that, if a duplicate entry exists, it must be in the preceding |
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* slot. |
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*/ |
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return num > 0 && cmp_rela(rela + num, rela + num - 1) == 0; |
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} |
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static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num, |
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Elf64_Word dstidx, Elf_Shdr *dstsec) |
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{ |
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unsigned int ret = 0; |
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Elf64_Sym *s; |
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int i; |
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for (i = 0; i < num; i++) { |
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u64 min_align; |
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switch (ELF64_R_TYPE(rela[i].r_info)) { |
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case R_AARCH64_JUMP26: |
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case R_AARCH64_CALL26: |
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if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) |
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break; |
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/* |
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* We only have to consider branch targets that resolve |
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* to symbols that are defined in a different section. |
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* This is not simply a heuristic, it is a fundamental |
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* limitation, since there is no guaranteed way to emit |
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* PLT entries sufficiently close to the branch if the |
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* section size exceeds the range of a branch |
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* instruction. So ignore relocations against defined |
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* symbols if they live in the same section as the |
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* relocation target. |
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*/ |
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s = syms + ELF64_R_SYM(rela[i].r_info); |
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if (s->st_shndx == dstidx) |
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break; |
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/* |
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* Jump relocations with non-zero addends against |
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* undefined symbols are supported by the ELF spec, but |
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* do not occur in practice (e.g., 'jump n bytes past |
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* the entry point of undefined function symbol f'). |
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* So we need to support them, but there is no need to |
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* take them into consideration when trying to optimize |
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* this code. So let's only check for duplicates when |
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* the addend is zero: this allows us to record the PLT |
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* entry address in the symbol table itself, rather than |
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* having to search the list for duplicates each time we |
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* emit one. |
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*/ |
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if (rela[i].r_addend != 0 || !duplicate_rel(rela, i)) |
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ret++; |
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break; |
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case R_AARCH64_ADR_PREL_PG_HI21_NC: |
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case R_AARCH64_ADR_PREL_PG_HI21: |
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if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) || |
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!cpus_have_const_cap(ARM64_WORKAROUND_843419)) |
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break; |
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/* |
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* Determine the minimal safe alignment for this ADRP |
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* instruction: the section alignment at which it is |
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* guaranteed not to appear at a vulnerable offset. |
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* |
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* This comes down to finding the least significant zero |
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* bit in bits [11:3] of the section offset, and |
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* increasing the section's alignment so that the |
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* resulting address of this instruction is guaranteed |
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* to equal the offset in that particular bit (as well |
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* as all less signficant bits). This ensures that the |
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* address modulo 4 KB != 0xfff8 or 0xfffc (which would |
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* have all ones in bits [11:3]) |
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*/ |
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min_align = 2ULL << ffz(rela[i].r_offset | 0x7); |
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/* |
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* Allocate veneer space for each ADRP that may appear |
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* at a vulnerable offset nonetheless. At relocation |
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* time, some of these will remain unused since some |
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* ADRP instructions can be patched to ADR instructions |
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* instead. |
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*/ |
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if (min_align > SZ_4K) |
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ret++; |
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else |
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dstsec->sh_addralign = max(dstsec->sh_addralign, |
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min_align); |
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break; |
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} |
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} |
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if (IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) && |
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cpus_have_const_cap(ARM64_WORKAROUND_843419)) |
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/* |
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* Add some slack so we can skip PLT slots that may trigger |
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* the erratum due to the placement of the ADRP instruction. |
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*/ |
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ret += DIV_ROUND_UP(ret, (SZ_4K / sizeof(struct plt_entry))); |
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return ret; |
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} |
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static bool branch_rela_needs_plt(Elf64_Sym *syms, Elf64_Rela *rela, |
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Elf64_Word dstidx) |
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{ |
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Elf64_Sym *s = syms + ELF64_R_SYM(rela->r_info); |
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if (s->st_shndx == dstidx) |
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return false; |
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return ELF64_R_TYPE(rela->r_info) == R_AARCH64_JUMP26 || |
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ELF64_R_TYPE(rela->r_info) == R_AARCH64_CALL26; |
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} |
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/* Group branch PLT relas at the front end of the array. */ |
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static int partition_branch_plt_relas(Elf64_Sym *syms, Elf64_Rela *rela, |
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int numrels, Elf64_Word dstidx) |
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{ |
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int i = 0, j = numrels - 1; |
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if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) |
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return 0; |
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while (i < j) { |
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if (branch_rela_needs_plt(syms, &rela[i], dstidx)) |
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i++; |
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else if (branch_rela_needs_plt(syms, &rela[j], dstidx)) |
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swap(rela[i], rela[j]); |
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else |
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j--; |
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} |
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return i; |
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} |
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int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, |
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char *secstrings, struct module *mod) |
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{ |
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unsigned long core_plts = 0; |
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unsigned long init_plts = 0; |
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Elf64_Sym *syms = NULL; |
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Elf_Shdr *pltsec, *tramp = NULL; |
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int i; |
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/* |
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* Find the empty .plt section so we can expand it to store the PLT |
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* entries. Record the symtab address as well. |
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*/ |
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for (i = 0; i < ehdr->e_shnum; i++) { |
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if (!strcmp(secstrings + sechdrs[i].sh_name, ".plt")) |
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mod->arch.core.plt_shndx = i; |
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else if (!strcmp(secstrings + sechdrs[i].sh_name, ".init.plt")) |
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mod->arch.init.plt_shndx = i; |
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else if (!strcmp(secstrings + sechdrs[i].sh_name, |
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".text.ftrace_trampoline")) |
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tramp = sechdrs + i; |
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else if (sechdrs[i].sh_type == SHT_SYMTAB) |
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syms = (Elf64_Sym *)sechdrs[i].sh_addr; |
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} |
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if (!mod->arch.core.plt_shndx || !mod->arch.init.plt_shndx) { |
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pr_err("%s: module PLT section(s) missing\n", mod->name); |
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return -ENOEXEC; |
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} |
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if (!syms) { |
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pr_err("%s: module symtab section missing\n", mod->name); |
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return -ENOEXEC; |
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} |
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for (i = 0; i < ehdr->e_shnum; i++) { |
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Elf64_Rela *rels = (void *)ehdr + sechdrs[i].sh_offset; |
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int nents, numrels = sechdrs[i].sh_size / sizeof(Elf64_Rela); |
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Elf64_Shdr *dstsec = sechdrs + sechdrs[i].sh_info; |
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if (sechdrs[i].sh_type != SHT_RELA) |
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continue; |
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/* ignore relocations that operate on non-exec sections */ |
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if (!(dstsec->sh_flags & SHF_EXECINSTR)) |
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continue; |
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/* |
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* sort branch relocations requiring a PLT by type, symbol index |
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* and addend |
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*/ |
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nents = partition_branch_plt_relas(syms, rels, numrels, |
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sechdrs[i].sh_info); |
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if (nents) |
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sort(rels, nents, sizeof(Elf64_Rela), cmp_rela, NULL); |
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if (!str_has_prefix(secstrings + dstsec->sh_name, ".init")) |
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core_plts += count_plts(syms, rels, numrels, |
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sechdrs[i].sh_info, dstsec); |
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else |
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init_plts += count_plts(syms, rels, numrels, |
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sechdrs[i].sh_info, dstsec); |
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} |
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pltsec = sechdrs + mod->arch.core.plt_shndx; |
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pltsec->sh_type = SHT_NOBITS; |
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pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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pltsec->sh_addralign = L1_CACHE_BYTES; |
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pltsec->sh_size = (core_plts + 1) * sizeof(struct plt_entry); |
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mod->arch.core.plt_num_entries = 0; |
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mod->arch.core.plt_max_entries = core_plts; |
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pltsec = sechdrs + mod->arch.init.plt_shndx; |
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pltsec->sh_type = SHT_NOBITS; |
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pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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pltsec->sh_addralign = L1_CACHE_BYTES; |
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pltsec->sh_size = (init_plts + 1) * sizeof(struct plt_entry); |
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mod->arch.init.plt_num_entries = 0; |
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mod->arch.init.plt_max_entries = init_plts; |
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if (tramp) { |
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tramp->sh_type = SHT_NOBITS; |
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tramp->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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tramp->sh_addralign = __alignof__(struct plt_entry); |
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tramp->sh_size = NR_FTRACE_PLTS * sizeof(struct plt_entry); |
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} |
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return 0; |
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}
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