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469 lines
14 KiB
469 lines
14 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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NetWinder Floating Point Emulator |
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(c) Rebel.COM, 1998,1999 |
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(c) Philip Blundell, 2001 |
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Direct questions, comments to Scott Bambrough <[email protected]> |
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*/ |
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#ifndef __FPOPCODE_H__ |
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#define __FPOPCODE_H__ |
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/* |
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ARM Floating Point Instruction Classes |
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| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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|c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT |
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|c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2) |
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| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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|c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO |
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|c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT |
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|c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons |
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| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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CPDT data transfer instructions |
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LDF, STF, LFM (copro 2), SFM (copro 2) |
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CPDO dyadic arithmetic instructions |
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ADF, MUF, SUF, RSF, DVF, RDF, |
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POW, RPW, RMF, FML, FDV, FRD, POL |
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CPDO monadic arithmetic instructions |
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MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP, |
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SIN, COS, TAN, ASN, ACS, ATN, URD, NRM |
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CPRT joint arithmetic/data transfer instructions |
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FIX (arithmetic followed by load/store) |
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FLT (load/store followed by arithmetic) |
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CMF, CNF CMFE, CNFE (comparisons) |
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WFS, RFS (write/read floating point status register) |
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WFC, RFC (write/read floating point control register) |
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cond condition codes |
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P pre/post index bit: 0 = postindex, 1 = preindex |
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U up/down bit: 0 = stack grows down, 1 = stack grows up |
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W write back bit: 1 = update base register (Rn) |
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L load/store bit: 0 = store, 1 = load |
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Rn base register |
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Rd destination/source register |
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Fd floating point destination register |
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Fn floating point source register |
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Fm floating point source register or floating point constant |
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uv transfer length (TABLE 1) |
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wx register count (TABLE 2) |
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abcd arithmetic opcode (TABLES 3 & 4) |
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ef destination size (rounding precision) (TABLE 5) |
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gh rounding mode (TABLE 6) |
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j dyadic/monadic bit: 0 = dyadic, 1 = monadic |
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i constant bit: 1 = constant (TABLE 6) |
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*/ |
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/* |
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TABLE 1 |
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+-------------------------+---+---+---------+---------+ |
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| Precision | u | v | FPSR.EP | length | |
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+-------------------------+---+---+---------+---------+ |
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| Single | 0 | 0 | x | 1 words | |
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| Double | 1 | 1 | x | 2 words | |
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| Extended | 1 | 1 | x | 3 words | |
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| Packed decimal | 1 | 1 | 0 | 3 words | |
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| Expanded packed decimal | 1 | 1 | 1 | 4 words | |
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+-------------------------+---+---+---------+---------+ |
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Note: x = don't care |
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*/ |
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/* |
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TABLE 2 |
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+---+---+---------------------------------+ |
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| w | x | Number of registers to transfer | |
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+---+---+---------------------------------+ |
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| 0 | 1 | 1 | |
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| 1 | 0 | 2 | |
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| 1 | 1 | 3 | |
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| 0 | 0 | 4 | |
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+---+---+---------------------------------+ |
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*/ |
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/* |
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TABLE 3: Dyadic Floating Point Opcodes |
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+---+---+---+---+----------+-----------------------+-----------------------+ |
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| a | b | c | d | Mnemonic | Description | Operation | |
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+---+---+---+---+----------+-----------------------+-----------------------+ |
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| 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm | |
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| 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm | |
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| 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm | |
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| 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn | |
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| 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm | |
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| 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn | |
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| 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm | |
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| 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn | |
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| 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) | |
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| 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm | |
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| 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm | |
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| 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn | |
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| 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) | |
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| 1 | 1 | 0 | 1 | | undefined instruction | trap | |
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| 1 | 1 | 1 | 0 | | undefined instruction | trap | |
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| 1 | 1 | 1 | 1 | | undefined instruction | trap | |
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+---+---+---+---+----------+-----------------------+-----------------------+ |
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Note: POW, RPW, POL are deprecated, and are available for backwards |
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compatibility only. |
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*/ |
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/* |
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TABLE 4: Monadic Floating Point Opcodes |
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+---+---+---+---+----------+-----------------------+-----------------------+ |
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| a | b | c | d | Mnemonic | Description | Operation | |
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+---+---+---+---+----------+-----------------------+-----------------------+ |
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| 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm | |
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| 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm | |
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| 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) | |
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| 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) | |
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| 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) | |
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| 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) | |
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| 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) | |
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| 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm | |
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| 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) | |
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| 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) | |
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| 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) | |
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| 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) | |
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| 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) | |
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| 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) | |
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| 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) | |
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| 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) | |
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+---+---+---+---+----------+-----------------------+-----------------------+ |
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Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are |
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available for backwards compatibility only. |
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*/ |
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/* |
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TABLE 5 |
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+-------------------------+---+---+ |
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| Rounding Precision | e | f | |
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+-------------------------+---+---+ |
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| IEEE Single precision | 0 | 0 | |
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| IEEE Double precision | 0 | 1 | |
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| IEEE Extended precision | 1 | 0 | |
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| undefined (trap) | 1 | 1 | |
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+-------------------------+---+---+ |
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*/ |
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/* |
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TABLE 5 |
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+---------------------------------+---+---+ |
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| Rounding Mode | g | h | |
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+---------------------------------+---+---+ |
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| Round to nearest (default) | 0 | 0 | |
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| Round toward plus infinity | 0 | 1 | |
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| Round toward negative infinity | 1 | 0 | |
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| Round toward zero | 1 | 1 | |
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+---------------------------------+---+---+ |
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*/ |
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/* |
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=== |
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=== Definitions for load and store instructions |
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=== |
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*/ |
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/* bit masks */ |
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#define BIT_PREINDEX 0x01000000 |
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#define BIT_UP 0x00800000 |
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#define BIT_WRITE_BACK 0x00200000 |
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#define BIT_LOAD 0x00100000 |
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/* masks for load/store */ |
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#define MASK_CPDT 0x0c000000 /* data processing opcode */ |
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#define MASK_OFFSET 0x000000ff |
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#define MASK_TRANSFER_LENGTH 0x00408000 |
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#define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH |
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#define MASK_COPROCESSOR 0x00000f00 |
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/* Tests for transfer length */ |
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#define TRANSFER_SINGLE 0x00000000 |
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#define TRANSFER_DOUBLE 0x00008000 |
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#define TRANSFER_EXTENDED 0x00400000 |
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#define TRANSFER_PACKED MASK_TRANSFER_LENGTH |
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/* Get the coprocessor number from the opcode. */ |
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#define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8) |
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/* Get the offset from the opcode. */ |
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#define getOffset(opcode) (opcode & MASK_OFFSET) |
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/* Tests for specific data transfer load/store opcodes. */ |
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#define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask)) |
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#define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD) |
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#define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT) |
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#define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) |
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#define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) |
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#define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1)) |
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#define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2)) |
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#define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0) |
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#define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0) |
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#define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0) |
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#define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0) |
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#define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0) |
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#define LOAD(opcode) ((opcode & BIT_LOAD) != 0) |
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#define STORE(opcode) ((opcode & BIT_LOAD) == 0) |
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/* |
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=== |
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=== Definitions for arithmetic instructions |
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=== |
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*/ |
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/* bit masks */ |
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#define BIT_MONADIC 0x00008000 |
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#define BIT_CONSTANT 0x00000008 |
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#define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0) |
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#define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0) |
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/* instruction identification masks */ |
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#define MASK_CPDO 0x0e000000 /* arithmetic opcode */ |
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#define MASK_ARITHMETIC_OPCODE 0x00f08000 |
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#define MASK_DESTINATION_SIZE 0x00080080 |
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/* dyadic arithmetic opcodes. */ |
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#define ADF_CODE 0x00000000 |
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#define MUF_CODE 0x00100000 |
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#define SUF_CODE 0x00200000 |
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#define RSF_CODE 0x00300000 |
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#define DVF_CODE 0x00400000 |
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#define RDF_CODE 0x00500000 |
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#define POW_CODE 0x00600000 |
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#define RPW_CODE 0x00700000 |
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#define RMF_CODE 0x00800000 |
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#define FML_CODE 0x00900000 |
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#define FDV_CODE 0x00a00000 |
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#define FRD_CODE 0x00b00000 |
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#define POL_CODE 0x00c00000 |
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/* 0x00d00000 is an invalid dyadic arithmetic opcode */ |
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/* 0x00e00000 is an invalid dyadic arithmetic opcode */ |
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/* 0x00f00000 is an invalid dyadic arithmetic opcode */ |
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/* monadic arithmetic opcodes. */ |
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#define MVF_CODE 0x00008000 |
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#define MNF_CODE 0x00108000 |
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#define ABS_CODE 0x00208000 |
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#define RND_CODE 0x00308000 |
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#define SQT_CODE 0x00408000 |
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#define LOG_CODE 0x00508000 |
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#define LGN_CODE 0x00608000 |
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#define EXP_CODE 0x00708000 |
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#define SIN_CODE 0x00808000 |
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#define COS_CODE 0x00908000 |
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#define TAN_CODE 0x00a08000 |
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#define ASN_CODE 0x00b08000 |
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#define ACS_CODE 0x00c08000 |
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#define ATN_CODE 0x00d08000 |
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#define URD_CODE 0x00e08000 |
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#define NRM_CODE 0x00f08000 |
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/* |
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=== |
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=== Definitions for register transfer and comparison instructions |
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=== |
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*/ |
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#define MASK_CPRT 0x0e000010 /* register transfer opcode */ |
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#define MASK_CPRT_CODE 0x00f00000 |
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#define FLT_CODE 0x00000000 |
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#define FIX_CODE 0x00100000 |
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#define WFS_CODE 0x00200000 |
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#define RFS_CODE 0x00300000 |
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#define WFC_CODE 0x00400000 |
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#define RFC_CODE 0x00500000 |
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#define CMF_CODE 0x00900000 |
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#define CNF_CODE 0x00b00000 |
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#define CMFE_CODE 0x00d00000 |
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#define CNFE_CODE 0x00f00000 |
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/* |
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=== |
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=== Common definitions |
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=== |
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*/ |
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/* register masks */ |
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#define MASK_Rd 0x0000f000 |
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#define MASK_Rn 0x000f0000 |
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#define MASK_Fd 0x00007000 |
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#define MASK_Fm 0x00000007 |
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#define MASK_Fn 0x00070000 |
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/* condition code masks */ |
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#define CC_MASK 0xf0000000 |
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#define CC_NEGATIVE 0x80000000 |
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#define CC_ZERO 0x40000000 |
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#define CC_CARRY 0x20000000 |
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#define CC_OVERFLOW 0x10000000 |
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#define CC_EQ 0x00000000 |
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#define CC_NE 0x10000000 |
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#define CC_CS 0x20000000 |
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#define CC_HS CC_CS |
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#define CC_CC 0x30000000 |
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#define CC_LO CC_CC |
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#define CC_MI 0x40000000 |
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#define CC_PL 0x50000000 |
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#define CC_VS 0x60000000 |
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#define CC_VC 0x70000000 |
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#define CC_HI 0x80000000 |
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#define CC_LS 0x90000000 |
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#define CC_GE 0xa0000000 |
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#define CC_LT 0xb0000000 |
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#define CC_GT 0xc0000000 |
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#define CC_LE 0xd0000000 |
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#define CC_AL 0xe0000000 |
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#define CC_NV 0xf0000000 |
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/* rounding masks/values */ |
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#define MASK_ROUNDING_MODE 0x00000060 |
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#define ROUND_TO_NEAREST 0x00000000 |
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#define ROUND_TO_PLUS_INFINITY 0x00000020 |
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#define ROUND_TO_MINUS_INFINITY 0x00000040 |
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#define ROUND_TO_ZERO 0x00000060 |
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#define MASK_ROUNDING_PRECISION 0x00080080 |
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#define ROUND_SINGLE 0x00000000 |
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#define ROUND_DOUBLE 0x00000080 |
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#define ROUND_EXTENDED 0x00080000 |
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/* Get the condition code from the opcode. */ |
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#define getCondition(opcode) (opcode >> 28) |
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/* Get the source register from the opcode. */ |
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#define getRn(opcode) ((opcode & MASK_Rn) >> 16) |
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/* Get the destination floating point register from the opcode. */ |
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#define getFd(opcode) ((opcode & MASK_Fd) >> 12) |
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/* Get the first source floating point register from the opcode. */ |
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#define getFn(opcode) ((opcode & MASK_Fn) >> 16) |
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/* Get the second source floating point register from the opcode. */ |
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#define getFm(opcode) (opcode & MASK_Fm) |
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/* Get the destination register from the opcode. */ |
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#define getRd(opcode) ((opcode & MASK_Rd) >> 12) |
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/* Get the rounding mode from the opcode. */ |
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#define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5) |
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#ifdef CONFIG_FPE_NWFPE_XP |
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static inline floatx80 __pure getExtendedConstant(const unsigned int nIndex) |
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{ |
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extern const floatx80 floatx80Constant[]; |
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return floatx80Constant[nIndex]; |
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} |
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#endif |
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static inline float64 __pure getDoubleConstant(const unsigned int nIndex) |
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{ |
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extern const float64 float64Constant[]; |
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return float64Constant[nIndex]; |
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} |
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static inline float32 __pure getSingleConstant(const unsigned int nIndex) |
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{ |
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extern const float32 float32Constant[]; |
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return float32Constant[nIndex]; |
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} |
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static inline unsigned int getTransferLength(const unsigned int opcode) |
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{ |
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unsigned int nRc; |
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switch (opcode & MASK_TRANSFER_LENGTH) { |
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case 0x00000000: |
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nRc = 1; |
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break; /* single precision */ |
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case 0x00008000: |
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nRc = 2; |
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break; /* double precision */ |
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case 0x00400000: |
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nRc = 3; |
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break; /* extended precision */ |
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default: |
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nRc = 0; |
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} |
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return (nRc); |
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} |
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static inline unsigned int getRegisterCount(const unsigned int opcode) |
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{ |
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unsigned int nRc; |
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switch (opcode & MASK_REGISTER_COUNT) { |
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case 0x00000000: |
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nRc = 4; |
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break; |
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case 0x00008000: |
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nRc = 1; |
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break; |
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case 0x00400000: |
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nRc = 2; |
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break; |
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case 0x00408000: |
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nRc = 3; |
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break; |
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default: |
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nRc = 0; |
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} |
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return (nRc); |
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} |
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static inline unsigned int getRoundingPrecision(const unsigned int opcode) |
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{ |
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unsigned int nRc; |
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switch (opcode & MASK_ROUNDING_PRECISION) { |
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case 0x00000000: |
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nRc = 1; |
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break; |
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case 0x00000080: |
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nRc = 2; |
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break; |
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case 0x00080000: |
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nRc = 3; |
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break; |
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default: |
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nRc = 0; |
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} |
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return (nRc); |
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} |
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static inline unsigned int getDestinationSize(const unsigned int opcode) |
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{ |
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unsigned int nRc; |
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switch (opcode & MASK_DESTINATION_SIZE) { |
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case 0x00000000: |
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nRc = typeSingle; |
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break; |
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case 0x00000080: |
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nRc = typeDouble; |
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break; |
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case 0x00080000: |
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nRc = typeExtended; |
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break; |
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default: |
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nRc = typeNone; |
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} |
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return (nRc); |
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} |
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extern const float64 float64Constant[]; |
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extern const float32 float32Constant[]; |
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#endif
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