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333 lines
7.7 KiB
333 lines
7.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Copyright 2010 Darius Augulis <[email protected]> |
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// Copyright 2008 Openmoko, Inc. |
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// Copyright 2008 Simtec Electronics |
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// Ben Dooks <[email protected]> |
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// http://armlinux.simtec.co.uk/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/fb.h> |
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#include <linux/gpio.h> |
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#include <linux/kernel.h> |
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#include <linux/list.h> |
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#include <linux/dm9000.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/platform_device.h> |
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#include <linux/serial_core.h> |
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#include <linux/serial_s3c.h> |
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#include <linux/types.h> |
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#include <asm/mach-types.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include "map.h" |
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#include "regs-gpio.h" |
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#include "gpio-samsung.h" |
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#include <mach/irqs.h> |
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#include <linux/soc/samsung/s3c-adc.h> |
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#include "cpu.h" |
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#include "devs.h" |
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#include "fb.h" |
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#include <linux/platform_data/mtd-nand-s3c2410.h> |
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#include <linux/platform_data/touchscreen-s3c2410.h> |
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#include <video/platform_lcd.h> |
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#include <video/samsung_fimd.h> |
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#include "s3c64xx.h" |
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#include "regs-modem-s3c64xx.h" |
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#include "regs-srom-s3c64xx.h" |
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#define UCON S3C2410_UCON_DEFAULT |
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#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) |
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#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) |
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static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = { |
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[0] = { |
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.hwport = 0, |
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.flags = 0, |
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.ucon = UCON, |
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.ulcon = ULCON, |
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.ufcon = UFCON, |
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}, |
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[1] = { |
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.hwport = 1, |
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.flags = 0, |
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.ucon = UCON, |
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.ulcon = ULCON, |
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.ufcon = UFCON, |
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}, |
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[2] = { |
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.hwport = 2, |
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.flags = 0, |
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.ucon = UCON, |
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.ulcon = ULCON, |
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.ufcon = UFCON, |
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}, |
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[3] = { |
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.hwport = 3, |
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.flags = 0, |
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.ucon = UCON, |
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.ulcon = ULCON, |
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.ufcon = UFCON, |
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}, |
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}; |
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/* DM9000AEP 10/100 ethernet controller */ |
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static struct resource real6410_dm9k_resource[] = { |
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[0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2), |
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[1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2), |
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[2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \ |
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| IORESOURCE_IRQ_HIGHLEVEL), |
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}; |
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static struct dm9000_plat_data real6410_dm9k_pdata = { |
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.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), |
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}; |
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static struct platform_device real6410_device_eth = { |
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.name = "dm9000", |
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.id = -1, |
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.num_resources = ARRAY_SIZE(real6410_dm9k_resource), |
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.resource = real6410_dm9k_resource, |
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.dev = { |
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.platform_data = &real6410_dm9k_pdata, |
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}, |
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}; |
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static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = { |
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.max_bpp = 32, |
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.default_bpp = 16, |
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.xres = 480, |
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.yres = 272, |
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}; |
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static struct fb_videomode real6410_lcd_type0_timing = { |
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/* 4.3" 480x272 */ |
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.left_margin = 3, |
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.right_margin = 2, |
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.upper_margin = 1, |
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.lower_margin = 1, |
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.hsync_len = 40, |
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.vsync_len = 1, |
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}; |
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static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = { |
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.max_bpp = 32, |
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.default_bpp = 16, |
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.xres = 800, |
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.yres = 480, |
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}; |
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static struct fb_videomode real6410_lcd_type1_timing = { |
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/* 7.0" 800x480 */ |
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.left_margin = 8, |
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.right_margin = 13, |
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.upper_margin = 7, |
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.lower_margin = 5, |
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.hsync_len = 3, |
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.vsync_len = 1, |
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.xres = 800, |
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.yres = 480, |
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}; |
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static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = { |
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{ |
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.setup_gpio = s3c64xx_fb_gpio_setup_24bpp, |
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.vtiming = &real6410_lcd_type0_timing, |
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.win[0] = &real6410_lcd_type0_fb_win, |
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.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, |
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.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, |
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}, { |
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.setup_gpio = s3c64xx_fb_gpio_setup_24bpp, |
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.vtiming = &real6410_lcd_type1_timing, |
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.win[0] = &real6410_lcd_type1_fb_win, |
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.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, |
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.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, |
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}, |
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{ }, |
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}; |
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static struct mtd_partition real6410_nand_part[] = { |
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[0] = { |
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.name = "uboot", |
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.size = SZ_1M, |
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.offset = 0, |
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}, |
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[1] = { |
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.name = "kernel", |
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.size = SZ_2M, |
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.offset = SZ_1M, |
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}, |
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[2] = { |
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.name = "rootfs", |
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.size = MTDPART_SIZ_FULL, |
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.offset = SZ_1M + SZ_2M, |
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}, |
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}; |
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static struct s3c2410_nand_set real6410_nand_sets[] = { |
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[0] = { |
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.name = "nand", |
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.nr_chips = 1, |
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.nr_partitions = ARRAY_SIZE(real6410_nand_part), |
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.partitions = real6410_nand_part, |
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}, |
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}; |
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static struct s3c2410_platform_nand real6410_nand_info = { |
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.tacls = 25, |
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.twrph0 = 55, |
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.twrph1 = 40, |
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.nr_sets = ARRAY_SIZE(real6410_nand_sets), |
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.sets = real6410_nand_sets, |
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.engine_type = NAND_ECC_ENGINE_TYPE_SOFT, |
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}; |
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static struct platform_device *real6410_devices[] __initdata = { |
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&real6410_device_eth, |
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&s3c_device_hsmmc0, |
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&s3c_device_hsmmc1, |
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&s3c_device_fb, |
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&s3c_device_nand, |
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&s3c_device_adc, |
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&s3c_device_ohci, |
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}; |
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static void __init real6410_map_io(void) |
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{ |
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u32 tmp; |
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s3c64xx_init_io(NULL, 0); |
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s3c24xx_init_clocks(12000000); |
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s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs)); |
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s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); |
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/* set the LCD type */ |
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tmp = __raw_readl(S3C64XX_SPCON); |
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tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; |
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tmp |= S3C64XX_SPCON_LCD_SEL_RGB; |
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__raw_writel(tmp, S3C64XX_SPCON); |
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/* remove the LCD bypass */ |
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tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); |
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tmp &= ~MIFPCON_LCD_BYPASS; |
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__raw_writel(tmp, S3C64XX_MODEM_MIFPCON); |
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} |
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/* |
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* real6410_features string |
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* |
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* 0-9 LCD configuration |
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* |
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*/ |
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static char real6410_features_str[12] __initdata = "0"; |
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static int __init real6410_features_setup(char *str) |
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{ |
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if (str) |
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strlcpy(real6410_features_str, str, |
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sizeof(real6410_features_str)); |
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return 1; |
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} |
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__setup("real6410=", real6410_features_setup); |
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#define FEATURE_SCREEN (1 << 0) |
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struct real6410_features_t { |
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int done; |
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int lcd_index; |
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}; |
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static void real6410_parse_features( |
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struct real6410_features_t *features, |
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const char *features_str) |
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{ |
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const char *fp = features_str; |
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features->done = 0; |
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features->lcd_index = 0; |
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while (*fp) { |
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char f = *fp++; |
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switch (f) { |
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case '0'...'9': /* tft screen */ |
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if (features->done & FEATURE_SCREEN) { |
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printk(KERN_INFO "REAL6410: '%c' ignored, " |
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"screen type already set\n", f); |
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} else { |
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int li = f - '0'; |
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if (li >= ARRAY_SIZE(real6410_lcd_pdata)) |
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printk(KERN_INFO "REAL6410: '%c' out " |
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"of range LCD mode\n", f); |
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else { |
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features->lcd_index = li; |
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} |
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} |
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features->done |= FEATURE_SCREEN; |
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break; |
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} |
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} |
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} |
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static void __init real6410_machine_init(void) |
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{ |
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u32 cs1; |
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struct real6410_features_t features = { 0 }; |
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printk(KERN_INFO "REAL6410: Option string real6410=%s\n", |
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real6410_features_str); |
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/* Parse the feature string */ |
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real6410_parse_features(&features, real6410_features_str); |
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printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n", |
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real6410_lcd_pdata[features.lcd_index].win[0]->xres, |
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real6410_lcd_pdata[features.lcd_index].win[0]->yres); |
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s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]); |
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s3c_nand_set_platdata(&real6410_nand_info); |
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s3c64xx_ts_set_platdata(NULL); |
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/* configure nCS1 width to 16 bits */ |
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cs1 = __raw_readl(S3C64XX_SROM_BW) & |
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~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); |
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cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | |
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(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | |
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(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << |
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S3C64XX_SROM_BW__NCS1__SHIFT; |
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__raw_writel(cs1, S3C64XX_SROM_BW); |
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/* set timing for nCS1 suitable for ethernet chip */ |
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__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | |
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(6 << S3C64XX_SROM_BCX__TACP__SHIFT) | |
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(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | |
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(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | |
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(13 << S3C64XX_SROM_BCX__TACC__SHIFT) | |
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(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | |
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(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); |
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gpio_request(S3C64XX_GPF(15), "LCD power"); |
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platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices)); |
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} |
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MACHINE_START(REAL6410, "REAL6410") |
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/* Maintainer: Darius Augulis <[email protected]> */ |
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.atag_offset = 0x100, |
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.nr_irqs = S3C64XX_NR_IRQS, |
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.init_irq = s3c6410_init_irq, |
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.map_io = real6410_map_io, |
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.init_machine = real6410_machine_init, |
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.init_time = s3c64xx_timer_init, |
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MACHINE_END
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