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278 lines
7.3 KiB
278 lines
7.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Copyright (c) 2006-2008 Simtec Electronics |
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// http://armlinux.simtec.co.uk/ |
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// Ben Dooks <[email protected]> |
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// |
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// S3C2412/S3C2443 (PL093 based) IO timing support |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <linux/cpufreq.h> |
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#include <linux/seq_file.h> |
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#include <linux/device.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/slab.h> |
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#include <linux/amba/pl093.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include "cpu.h" |
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#include <linux/soc/samsung/s3c-cpufreq-core.h> |
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#include "s3c2412.h" |
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#define print_ns(x) ((x) / 10), ((x) % 10) |
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/** |
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* s3c2412_print_timing - print timing information via printk. |
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* @pfx: The prefix to print each line with. |
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* @iot: The IO timing information |
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*/ |
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static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot) |
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{ |
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struct s3c2412_iobank_timing *bt; |
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unsigned int bank; |
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for (bank = 0; bank < MAX_BANKS; bank++) { |
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bt = iot->bank[bank].io_2412; |
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if (!bt) |
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continue; |
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printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" |
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"wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, |
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print_ns(bt->idcy), |
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print_ns(bt->wstrd), |
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print_ns(bt->wstwr), |
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print_ns(bt->wstoen), |
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print_ns(bt->wstwen), |
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print_ns(bt->wstbrd)); |
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} |
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} |
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/** |
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* to_div - turn a cycle length into a divisor setting. |
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* @cyc_tns: The cycle time in 10ths of nanoseconds. |
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* @clk_tns: The clock period in 10ths of nanoseconds. |
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*/ |
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static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns) |
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{ |
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return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0; |
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} |
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/** |
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* calc_timing - calculate timing divisor value and check in range. |
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* @hwtm: The hardware timing in 10ths of nanoseconds. |
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* @clk_tns: The clock period in 10ths of nanoseconds. |
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* @err: Pointer to err variable to update in event of failure. |
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*/ |
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static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns, |
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unsigned int *err) |
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{ |
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unsigned int ret = to_div(hwtm, clk_tns); |
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if (ret > 0xf) |
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*err = -EINVAL; |
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return ret; |
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} |
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/** |
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* s3c2412_calc_bank - calculate the bank divisor settings. |
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* @cfg: The current frequency configuration. |
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* @bt: The bank timing. |
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*/ |
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static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg, |
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struct s3c2412_iobank_timing *bt) |
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{ |
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unsigned int hclk = cfg->freq.hclk_tns; |
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int err = 0; |
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bt->smbidcyr = calc_timing(bt->idcy, hclk, &err); |
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bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err); |
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bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err); |
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bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err); |
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bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err); |
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bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err); |
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return err; |
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} |
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/** |
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* s3c2412_iotiming_debugfs - debugfs show io bank timing information |
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* @seq: The seq_file to write output to using seq_printf(). |
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* @cfg: The current configuration. |
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* @iob: The IO bank information to decode. |
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*/ |
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void s3c2412_iotiming_debugfs(struct seq_file *seq, |
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struct s3c_cpufreq_config *cfg, |
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union s3c_iobank *iob) |
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{ |
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struct s3c2412_iobank_timing *bt = iob->io_2412; |
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seq_printf(seq, |
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"\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d" |
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"wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", |
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print_ns(bt->idcy), |
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print_ns(bt->wstrd), |
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print_ns(bt->wstwr), |
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print_ns(bt->wstoen), |
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print_ns(bt->wstwen), |
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print_ns(bt->wstbrd)); |
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} |
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/** |
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* s3c2412_iotiming_calc - calculate all the bank divisor settings. |
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* @cfg: The current frequency configuration. |
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* @iot: The bank timing information. |
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* |
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* Calculate the timing information for all the banks that are |
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* configured as IO, using s3c2412_calc_bank(). |
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*/ |
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int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *iot) |
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{ |
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struct s3c2412_iobank_timing *bt; |
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int bank; |
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int ret; |
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for (bank = 0; bank < MAX_BANKS; bank++) { |
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bt = iot->bank[bank].io_2412; |
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if (!bt) |
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continue; |
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ret = s3c2412_calc_bank(cfg, bt); |
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if (ret) { |
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printk(KERN_ERR "%s: cannot calculate bank %d io\n", |
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__func__, bank); |
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goto err; |
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} |
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} |
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return 0; |
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err: |
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return ret; |
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} |
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/** |
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* s3c2412_iotiming_set - set the timing information |
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* @cfg: The current frequency configuration. |
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* @iot: The bank timing information. |
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* |
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* Set the IO bank information from the details calculated earlier from |
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* calling s3c2412_iotiming_calc(). |
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*/ |
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void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *iot) |
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{ |
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struct s3c2412_iobank_timing *bt; |
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void __iomem *regs; |
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int bank; |
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/* set the io timings from the specifier */ |
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for (bank = 0; bank < MAX_BANKS; bank++) { |
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bt = iot->bank[bank].io_2412; |
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if (!bt) |
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continue; |
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regs = S3C2412_SSMC_BANK(bank); |
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__raw_writel(bt->smbidcyr, regs + SMBIDCYR); |
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__raw_writel(bt->smbwstrd, regs + SMBWSTRDR); |
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__raw_writel(bt->smbwstwr, regs + SMBWSTWRR); |
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__raw_writel(bt->smbwstoen, regs + SMBWSTOENR); |
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__raw_writel(bt->smbwstwen, regs + SMBWSTWENR); |
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__raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR); |
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} |
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} |
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static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg) |
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{ |
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return (reg & 0xf) * clock; |
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} |
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static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg, |
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struct s3c2412_iobank_timing *bt, |
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unsigned int bank) |
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{ |
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unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */ |
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void __iomem *regs = S3C2412_SSMC_BANK(bank); |
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bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR)); |
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bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR)); |
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bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR)); |
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bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR)); |
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bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR)); |
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} |
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/** |
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* bank_is_io - return true if bank is (possibly) IO. |
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* @bank: The bank number. |
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* @bankcfg: The value of S3C2412_EBI_BANKCFG. |
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*/ |
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static inline bool bank_is_io(unsigned int bank, u32 bankcfg) |
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{ |
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if (bank < 2) |
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return true; |
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return !(bankcfg & (1 << bank)); |
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} |
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int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *timings) |
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{ |
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struct s3c2412_iobank_timing *bt; |
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u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG); |
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unsigned int bank; |
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/* look through all banks to see what is currently set. */ |
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for (bank = 0; bank < MAX_BANKS; bank++) { |
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if (!bank_is_io(bank, bankcfg)) |
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continue; |
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bt = kzalloc(sizeof(*bt), GFP_KERNEL); |
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if (!bt) |
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return -ENOMEM; |
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timings->bank[bank].io_2412 = bt; |
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s3c2412_iotiming_getbank(cfg, bt, bank); |
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} |
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s3c2412_print_timing("get", timings); |
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return 0; |
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} |
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/* this is in here as it is so small, it doesn't currently warrant a file |
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* to itself. We expect that any s3c24xx needing this is going to also |
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* need the iotiming support. |
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*/ |
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void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) |
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{ |
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struct s3c_cpufreq_board *board = cfg->board; |
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u32 refresh; |
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WARN_ON(board == NULL); |
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/* Reduce both the refresh time (in ns) and the frequency (in MHz) |
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* down to ensure that we do not overflow 32 bit numbers. |
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* |
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* This should work for HCLK up to 133MHz and refresh period up |
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* to 30usec. |
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*/ |
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refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); |
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refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ |
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refresh &= ((1 << 16) - 1); |
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s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); |
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__raw_writel(refresh, S3C2412_REFRESH); |
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}
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