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420 lines
11 KiB
420 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
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*/ |
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#include <linux/suspend.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/export.h> |
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#include <linux/genalloc.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <asm/cacheflush.h> |
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#include <asm/fncpy.h> |
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#include <asm/system_misc.h> |
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#include <asm/tlbflush.h> |
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#include "common.h" |
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#include "cpuidle.h" |
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#include "hardware.h" |
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#define MXC_CCM_CLPCR 0x54 |
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#define MXC_CCM_CLPCR_LPM_OFFSET 0 |
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#define MXC_CCM_CLPCR_LPM_MASK 0x3 |
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#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 |
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#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) |
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#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) |
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#define MXC_CORTEXA8_PLAT_LPC 0xc |
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#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) |
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#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) |
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#define MXC_SRPG_NEON_SRPGCR 0x280 |
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#define MXC_SRPG_ARM_SRPGCR 0x2a0 |
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#define MXC_SRPG_EMPGC0_SRPGCR 0x2c0 |
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#define MXC_SRPG_EMPGC1_SRPGCR 0x2d0 |
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#define MXC_SRPGCR_PCR 1 |
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/* |
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* The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit. |
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* This is also the lowest power state possible without affecting |
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* non-cpu parts of the system. For these reasons, imx5 should default |
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* to always using this state for cpu idling. The PM_SUSPEND_STANDBY also |
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* uses this state and needs to take no action when registers remain confgiured |
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* for this state. |
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*/ |
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#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF |
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struct imx5_suspend_io_state { |
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u32 offset; |
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u32 clear; |
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u32 set; |
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u32 saved_value; |
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}; |
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struct imx5_pm_data { |
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phys_addr_t ccm_addr; |
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phys_addr_t cortex_addr; |
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phys_addr_t gpc_addr; |
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phys_addr_t m4if_addr; |
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phys_addr_t iomuxc_addr; |
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void (*suspend_asm)(void __iomem *ocram_vbase); |
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const u32 *suspend_asm_sz; |
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const struct imx5_suspend_io_state *suspend_io_config; |
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int suspend_io_count; |
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}; |
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static const struct imx5_suspend_io_state imx53_suspend_io_config[] = { |
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#define MX53_DSE_HIGHZ_MASK (0x7 << 19) |
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{.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */ |
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{.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */ |
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{.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */ |
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{.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */ |
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{.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */ |
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{.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */ |
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{.offset = 0x578, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_0 */ |
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{.offset = 0x570, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_1 */ |
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{.offset = 0x580, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT0 */ |
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{.offset = 0x564, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT1 */ |
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{.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */ |
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{.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */ |
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{.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */ |
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{.offset = 0x558, .clear = MX53_DSE_HIGHZ_MASK}, /* SDSQ3 */ |
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{.offset = 0x6f0, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_ADDS */ |
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{.offset = 0x718, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_BODS */ |
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{.offset = 0x71c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B1DS */ |
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{.offset = 0x728, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B2DS */ |
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{.offset = 0x72c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B3DS */ |
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/* Controls the CKE signal which is required to leave self refresh */ |
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{.offset = 0x720, .clear = MX53_DSE_HIGHZ_MASK, .set = 1 << 19}, /* CTLDS */ |
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}; |
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static const struct imx5_pm_data imx51_pm_data __initconst = { |
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.ccm_addr = 0x73fd4000, |
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.cortex_addr = 0x83fa0000, |
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.gpc_addr = 0x73fd8000, |
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}; |
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static const struct imx5_pm_data imx53_pm_data __initconst = { |
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.ccm_addr = 0x53fd4000, |
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.cortex_addr = 0x63fa0000, |
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.gpc_addr = 0x53fd8000, |
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.m4if_addr = 0x63fd8000, |
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.iomuxc_addr = 0x53fa8000, |
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.suspend_asm = &imx53_suspend, |
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.suspend_asm_sz = &imx53_suspend_sz, |
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.suspend_io_config = imx53_suspend_io_config, |
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.suspend_io_count = ARRAY_SIZE(imx53_suspend_io_config), |
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}; |
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#define MX5_MAX_SUSPEND_IOSTATE ARRAY_SIZE(imx53_suspend_io_config) |
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/* |
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* This structure is for passing necessary data for low level ocram |
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* suspend code(arch/arm/mach-imx/suspend-imx53.S), if this struct |
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* definition is changed, the offset definition in that file |
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* must be also changed accordingly otherwise, the suspend to ocram |
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* function will be broken! |
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*/ |
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struct imx5_cpu_suspend_info { |
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void __iomem *m4if_base; |
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void __iomem *iomuxc_base; |
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u32 io_count; |
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struct imx5_suspend_io_state io_state[MX5_MAX_SUSPEND_IOSTATE]; |
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} __aligned(8); |
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static void __iomem *ccm_base; |
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static void __iomem *cortex_base; |
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static void __iomem *gpc_base; |
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static void __iomem *suspend_ocram_base; |
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static void (*imx5_suspend_in_ocram_fn)(void __iomem *ocram_vbase); |
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/* |
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* set cpu low power mode before WFI instruction. This function is called |
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* mx5 because it can be used for mx51, and mx53. |
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*/ |
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static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) |
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{ |
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u32 plat_lpc, arm_srpgcr, ccm_clpcr; |
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u32 empgc0, empgc1; |
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int stop_mode = 0; |
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/* always allow platform to issue a deep sleep mode request */ |
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plat_lpc = imx_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & |
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~(MXC_CORTEXA8_PLAT_LPC_DSM); |
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ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & |
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~(MXC_CCM_CLPCR_LPM_MASK); |
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arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & |
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~(MXC_SRPGCR_PCR); |
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empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & |
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~(MXC_SRPGCR_PCR); |
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empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & |
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~(MXC_SRPGCR_PCR); |
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switch (mode) { |
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case WAIT_CLOCKED: |
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break; |
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case WAIT_UNCLOCKED: |
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ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; |
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break; |
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case WAIT_UNCLOCKED_POWER_OFF: |
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case STOP_POWER_OFF: |
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plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM |
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| MXC_CORTEXA8_PLAT_LPC_DBG_DSM; |
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if (mode == WAIT_UNCLOCKED_POWER_OFF) { |
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ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; |
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ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; |
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ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; |
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stop_mode = 0; |
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} else { |
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ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; |
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ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; |
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ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; |
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ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; |
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stop_mode = 1; |
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} |
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arm_srpgcr |= MXC_SRPGCR_PCR; |
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break; |
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case STOP_POWER_ON: |
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ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; |
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break; |
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default: |
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printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); |
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return; |
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} |
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imx_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC); |
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imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); |
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imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); |
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imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); |
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if (stop_mode) { |
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empgc0 |= MXC_SRPGCR_PCR; |
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empgc1 |= MXC_SRPGCR_PCR; |
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imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); |
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imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); |
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} |
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} |
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static int mx5_suspend_enter(suspend_state_t state) |
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{ |
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switch (state) { |
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case PM_SUSPEND_MEM: |
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mx5_cpu_lp_set(STOP_POWER_OFF); |
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break; |
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case PM_SUSPEND_STANDBY: |
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/* DEFAULT_IDLE_STATE already configured */ |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (state == PM_SUSPEND_MEM) { |
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local_flush_tlb_all(); |
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flush_cache_all(); |
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/*clear the EMPGC0/1 bits */ |
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imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); |
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imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); |
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if (imx5_suspend_in_ocram_fn) |
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imx5_suspend_in_ocram_fn(suspend_ocram_base); |
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else |
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cpu_do_idle(); |
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} else { |
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cpu_do_idle(); |
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} |
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/* return registers to default idle state */ |
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mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); |
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return 0; |
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} |
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static int mx5_pm_valid(suspend_state_t state) |
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{ |
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return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); |
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} |
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static const struct platform_suspend_ops mx5_suspend_ops = { |
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.valid = mx5_pm_valid, |
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.enter = mx5_suspend_enter, |
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}; |
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static inline int imx5_cpu_do_idle(void) |
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{ |
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int ret = tzic_enable_wake(); |
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if (likely(!ret)) |
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cpu_do_idle(); |
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return ret; |
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} |
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static void imx5_pm_idle(void) |
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{ |
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imx5_cpu_do_idle(); |
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} |
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static int __init imx_suspend_alloc_ocram( |
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size_t size, |
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void __iomem **virt_out, |
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phys_addr_t *phys_out) |
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{ |
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struct device_node *node; |
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struct platform_device *pdev; |
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struct gen_pool *ocram_pool; |
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unsigned long ocram_base; |
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void __iomem *virt; |
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phys_addr_t phys; |
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int ret = 0; |
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/* Copied from imx6: TODO factorize */ |
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node = of_find_compatible_node(NULL, NULL, "mmio-sram"); |
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if (!node) { |
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pr_warn("%s: failed to find ocram node!\n", __func__); |
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return -ENODEV; |
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} |
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pdev = of_find_device_by_node(node); |
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if (!pdev) { |
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pr_warn("%s: failed to find ocram device!\n", __func__); |
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ret = -ENODEV; |
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goto put_node; |
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} |
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ocram_pool = gen_pool_get(&pdev->dev, NULL); |
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if (!ocram_pool) { |
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pr_warn("%s: ocram pool unavailable!\n", __func__); |
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ret = -ENODEV; |
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goto put_device; |
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} |
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ocram_base = gen_pool_alloc(ocram_pool, size); |
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if (!ocram_base) { |
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pr_warn("%s: unable to alloc ocram!\n", __func__); |
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ret = -ENOMEM; |
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goto put_device; |
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} |
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phys = gen_pool_virt_to_phys(ocram_pool, ocram_base); |
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virt = __arm_ioremap_exec(phys, size, false); |
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if (phys_out) |
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*phys_out = phys; |
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if (virt_out) |
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*virt_out = virt; |
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put_device: |
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put_device(&pdev->dev); |
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put_node: |
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of_node_put(node); |
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return ret; |
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} |
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static int __init imx5_suspend_init(const struct imx5_pm_data *soc_data) |
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{ |
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struct imx5_cpu_suspend_info *suspend_info; |
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int ret; |
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/* Need this to avoid compile error due to const typeof in fncpy.h */ |
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void (*suspend_asm)(void __iomem *) = soc_data->suspend_asm; |
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if (!suspend_asm) |
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return 0; |
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if (!soc_data->suspend_asm_sz || !*soc_data->suspend_asm_sz) |
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return -EINVAL; |
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ret = imx_suspend_alloc_ocram( |
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*soc_data->suspend_asm_sz + sizeof(*suspend_info), |
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&suspend_ocram_base, NULL); |
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if (ret) |
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return ret; |
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suspend_info = suspend_ocram_base; |
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suspend_info->io_count = soc_data->suspend_io_count; |
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memcpy(suspend_info->io_state, soc_data->suspend_io_config, |
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sizeof(*suspend_info->io_state) * soc_data->suspend_io_count); |
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suspend_info->m4if_base = ioremap(soc_data->m4if_addr, SZ_16K); |
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if (!suspend_info->m4if_base) { |
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ret = -ENOMEM; |
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goto failed_map_m4if; |
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} |
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suspend_info->iomuxc_base = ioremap(soc_data->iomuxc_addr, SZ_16K); |
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if (!suspend_info->iomuxc_base) { |
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ret = -ENOMEM; |
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goto failed_map_iomuxc; |
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} |
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imx5_suspend_in_ocram_fn = fncpy( |
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suspend_ocram_base + sizeof(*suspend_info), |
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suspend_asm, |
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*soc_data->suspend_asm_sz); |
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return 0; |
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failed_map_iomuxc: |
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iounmap(suspend_info->m4if_base); |
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failed_map_m4if: |
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return ret; |
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} |
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static int __init imx5_pm_common_init(const struct imx5_pm_data *data) |
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{ |
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int ret; |
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struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); |
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if (IS_ERR(gpc_dvfs_clk)) |
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return PTR_ERR(gpc_dvfs_clk); |
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ret = clk_prepare_enable(gpc_dvfs_clk); |
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if (ret) |
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return ret; |
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arm_pm_idle = imx5_pm_idle; |
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ccm_base = ioremap(data->ccm_addr, SZ_16K); |
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cortex_base = ioremap(data->cortex_addr, SZ_16K); |
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gpc_base = ioremap(data->gpc_addr, SZ_16K); |
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WARN_ON(!ccm_base || !cortex_base || !gpc_base); |
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/* Set the registers to the default cpu idle state. */ |
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mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); |
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ret = imx5_cpuidle_init(); |
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if (ret) |
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pr_warn("%s: cpuidle init failed %d\n", __func__, ret); |
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ret = imx5_suspend_init(data); |
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if (ret) |
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pr_warn("%s: No DDR LPM support with suspend %d!\n", |
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__func__, ret); |
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suspend_set_ops(&mx5_suspend_ops); |
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return 0; |
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} |
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void __init imx51_pm_init(void) |
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{ |
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if (IS_ENABLED(CONFIG_SOC_IMX51)) |
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imx5_pm_common_init(&imx51_pm_data); |
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} |
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void __init imx53_pm_init(void) |
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{ |
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if (IS_ENABLED(CONFIG_SOC_IMX53)) |
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imx5_pm_common_init(&imx53_pm_data); |
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}
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