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590 lines
19 KiB
590 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* ARMv6 Performance counter handling code. |
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* |
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* Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles |
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* |
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* ARMv6 has 2 configurable performance counters and a single cycle counter. |
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* They all share a single reset bit but can be written to zero so we can use |
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* that for a reset. |
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* |
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* The counters can't be individually enabled or disabled so when we remove |
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* one event and replace it with another we could get spurious counts from the |
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* wrong event. However, we can take advantage of the fact that the |
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* performance counters can export events to the event bus, and the event bus |
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* itself can be monitored. This requires that we *don't* export the events to |
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* the event bus. The procedure for disabling a configurable counter is: |
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* - change the counter to count the ETMEXTOUT[0] signal (0x20). This |
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* effectively stops the counter from counting. |
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* - disable the counter's interrupt generation (each counter has it's |
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* own interrupt enable bit). |
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* Once stopped, the counter value can be written as 0 to reset. |
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* |
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* To enable a counter: |
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* - enable the counter's interrupt generation. |
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* - set the new event type. |
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* |
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* Note: the dedicated cycle counter only counts cycles and can't be |
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* enabled/disabled independently of the others. When we want to disable the |
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* cycle counter, we have to just disable the interrupt reporting and start |
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* ignoring that counter. When re-enabling, we have to reset the value and |
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* enable the interrupt. |
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*/ |
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|
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) |
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|
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#include <asm/cputype.h> |
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#include <asm/irq_regs.h> |
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|
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#include <linux/of.h> |
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#include <linux/perf/arm_pmu.h> |
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#include <linux/platform_device.h> |
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enum armv6_perf_types { |
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ARMV6_PERFCTR_ICACHE_MISS = 0x0, |
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ARMV6_PERFCTR_IBUF_STALL = 0x1, |
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ARMV6_PERFCTR_DDEP_STALL = 0x2, |
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ARMV6_PERFCTR_ITLB_MISS = 0x3, |
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ARMV6_PERFCTR_DTLB_MISS = 0x4, |
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ARMV6_PERFCTR_BR_EXEC = 0x5, |
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ARMV6_PERFCTR_BR_MISPREDICT = 0x6, |
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ARMV6_PERFCTR_INSTR_EXEC = 0x7, |
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ARMV6_PERFCTR_DCACHE_HIT = 0x9, |
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ARMV6_PERFCTR_DCACHE_ACCESS = 0xA, |
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ARMV6_PERFCTR_DCACHE_MISS = 0xB, |
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ARMV6_PERFCTR_DCACHE_WBACK = 0xC, |
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ARMV6_PERFCTR_SW_PC_CHANGE = 0xD, |
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ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF, |
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ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10, |
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ARMV6_PERFCTR_LSU_FULL_STALL = 0x11, |
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ARMV6_PERFCTR_WBUF_DRAINED = 0x12, |
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ARMV6_PERFCTR_CPU_CYCLES = 0xFF, |
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ARMV6_PERFCTR_NOP = 0x20, |
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}; |
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enum armv6_counters { |
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ARMV6_CYCLE_COUNTER = 0, |
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ARMV6_COUNTER0, |
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ARMV6_COUNTER1, |
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}; |
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|
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/* |
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* The hardware events that we support. We do support cache operations but |
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* we have harvard caches and no way to combine instruction and data |
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* accesses/misses in hardware. |
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*/ |
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static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { |
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PERF_MAP_ALL_UNSUPPORTED, |
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, |
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, |
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, |
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, |
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL, |
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL, |
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}; |
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static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
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[PERF_COUNT_HW_CACHE_OP_MAX] |
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
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PERF_CACHE_MAP_ALL_UNSUPPORTED, |
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|
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/* |
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* The performance counters don't differentiate between read and write |
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* accesses/misses so this isn't strictly correct, but it's the best we |
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* can do. Writes and reads get combined. |
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*/ |
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[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, |
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[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, |
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[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, |
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[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, |
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[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, |
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|
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/* |
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* The ARM performance counters can count micro DTLB misses, micro ITLB |
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* misses and main TLB misses. There isn't an event for TLB misses, so |
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* use the micro misses here and if users want the main TLB misses they |
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* can use a raw counter. |
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*/ |
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[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, |
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[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, |
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[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, |
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[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, |
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}; |
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enum armv6mpcore_perf_types { |
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ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0, |
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ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1, |
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ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2, |
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ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3, |
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ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4, |
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ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5, |
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ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6, |
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ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7, |
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ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8, |
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ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA, |
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ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB, |
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ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC, |
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ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD, |
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ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE, |
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ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF, |
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ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10, |
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ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11, |
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ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12, |
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ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13, |
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ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF, |
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}; |
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|
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/* |
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* The hardware events that we support. We do support cache operations but |
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* we have harvard caches and no way to combine instruction and data |
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* accesses/misses in hardware. |
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*/ |
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static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { |
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PERF_MAP_ALL_UNSUPPORTED, |
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, |
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, |
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, |
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, |
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL, |
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL, |
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}; |
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static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
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[PERF_COUNT_HW_CACHE_OP_MAX] |
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
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PERF_CACHE_MAP_ALL_UNSUPPORTED, |
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[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS, |
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[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS, |
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[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS, |
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[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS, |
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[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, |
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/* |
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* The ARM performance counters can count micro DTLB misses, micro ITLB |
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* misses and main TLB misses. There isn't an event for TLB misses, so |
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* use the micro misses here and if users want the main TLB misses they |
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* can use a raw counter. |
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*/ |
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[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, |
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[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, |
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[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, |
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[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, |
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}; |
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static inline unsigned long |
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armv6_pmcr_read(void) |
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{ |
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u32 val; |
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asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); |
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return val; |
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} |
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static inline void |
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armv6_pmcr_write(unsigned long val) |
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{ |
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asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); |
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} |
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#define ARMV6_PMCR_ENABLE (1 << 0) |
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#define ARMV6_PMCR_CTR01_RESET (1 << 1) |
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#define ARMV6_PMCR_CCOUNT_RESET (1 << 2) |
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#define ARMV6_PMCR_CCOUNT_DIV (1 << 3) |
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#define ARMV6_PMCR_COUNT0_IEN (1 << 4) |
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#define ARMV6_PMCR_COUNT1_IEN (1 << 5) |
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#define ARMV6_PMCR_CCOUNT_IEN (1 << 6) |
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#define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8) |
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#define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9) |
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#define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10) |
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#define ARMV6_PMCR_EVT_COUNT0_SHIFT 20 |
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#define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
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#define ARMV6_PMCR_EVT_COUNT1_SHIFT 12 |
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#define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
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#define ARMV6_PMCR_OVERFLOWED_MASK \ |
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(ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \ |
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ARMV6_PMCR_CCOUNT_OVERFLOW) |
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static inline int |
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armv6_pmcr_has_overflowed(unsigned long pmcr) |
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{ |
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return pmcr & ARMV6_PMCR_OVERFLOWED_MASK; |
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} |
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static inline int |
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armv6_pmcr_counter_has_overflowed(unsigned long pmcr, |
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enum armv6_counters counter) |
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{ |
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int ret = 0; |
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if (ARMV6_CYCLE_COUNTER == counter) |
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ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW; |
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else if (ARMV6_COUNTER0 == counter) |
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ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW; |
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else if (ARMV6_COUNTER1 == counter) |
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ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW; |
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else |
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WARN_ONCE(1, "invalid counter number (%d)\n", counter); |
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return ret; |
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} |
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static inline u64 armv6pmu_read_counter(struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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int counter = hwc->idx; |
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unsigned long value = 0; |
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if (ARMV6_CYCLE_COUNTER == counter) |
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asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value)); |
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else if (ARMV6_COUNTER0 == counter) |
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asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value)); |
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else if (ARMV6_COUNTER1 == counter) |
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asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value)); |
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else |
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WARN_ONCE(1, "invalid counter number (%d)\n", counter); |
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return value; |
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} |
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static inline void armv6pmu_write_counter(struct perf_event *event, u64 value) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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int counter = hwc->idx; |
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if (ARMV6_CYCLE_COUNTER == counter) |
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asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value)); |
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else if (ARMV6_COUNTER0 == counter) |
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asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value)); |
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else if (ARMV6_COUNTER1 == counter) |
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asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value)); |
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else |
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WARN_ONCE(1, "invalid counter number (%d)\n", counter); |
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} |
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static void armv6pmu_enable_event(struct perf_event *event) |
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{ |
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unsigned long val, mask, evt, flags; |
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struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
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struct hw_perf_event *hwc = &event->hw; |
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
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int idx = hwc->idx; |
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if (ARMV6_CYCLE_COUNTER == idx) { |
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mask = 0; |
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evt = ARMV6_PMCR_CCOUNT_IEN; |
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} else if (ARMV6_COUNTER0 == idx) { |
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mask = ARMV6_PMCR_EVT_COUNT0_MASK; |
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evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | |
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ARMV6_PMCR_COUNT0_IEN; |
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} else if (ARMV6_COUNTER1 == idx) { |
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mask = ARMV6_PMCR_EVT_COUNT1_MASK; |
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evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | |
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ARMV6_PMCR_COUNT1_IEN; |
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} else { |
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WARN_ONCE(1, "invalid counter number (%d)\n", idx); |
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return; |
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} |
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/* |
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* Mask out the current event and set the counter to count the event |
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* that we're interested in. |
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*/ |
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raw_spin_lock_irqsave(&events->pmu_lock, flags); |
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val = armv6_pmcr_read(); |
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val &= ~mask; |
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val |= evt; |
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armv6_pmcr_write(val); |
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
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} |
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static irqreturn_t |
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armv6pmu_handle_irq(struct arm_pmu *cpu_pmu) |
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{ |
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unsigned long pmcr = armv6_pmcr_read(); |
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struct perf_sample_data data; |
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struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); |
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struct pt_regs *regs; |
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int idx; |
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if (!armv6_pmcr_has_overflowed(pmcr)) |
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return IRQ_NONE; |
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regs = get_irq_regs(); |
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/* |
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* The interrupts are cleared by writing the overflow flags back to |
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* the control register. All of the other bits don't have any effect |
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* if they are rewritten, so write the whole value back. |
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*/ |
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armv6_pmcr_write(pmcr); |
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for (idx = 0; idx < cpu_pmu->num_events; ++idx) { |
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struct perf_event *event = cpuc->events[idx]; |
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struct hw_perf_event *hwc; |
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/* Ignore if we don't have an event. */ |
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if (!event) |
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continue; |
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/* |
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* We have a single interrupt for all counters. Check that |
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* each counter has overflowed before we process it. |
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*/ |
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if (!armv6_pmcr_counter_has_overflowed(pmcr, idx)) |
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continue; |
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hwc = &event->hw; |
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armpmu_event_update(event); |
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perf_sample_data_init(&data, 0, hwc->last_period); |
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if (!armpmu_event_set_period(event)) |
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continue; |
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if (perf_event_overflow(event, &data, regs)) |
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cpu_pmu->disable(event); |
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} |
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/* |
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* Handle the pending perf events. |
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* |
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* Note: this call *must* be run with interrupts disabled. For |
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* platforms that can have the PMU interrupts raised as an NMI, this |
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* will not work. |
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*/ |
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irq_work_run(); |
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return IRQ_HANDLED; |
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} |
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static void armv6pmu_start(struct arm_pmu *cpu_pmu) |
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{ |
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unsigned long flags, val; |
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
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raw_spin_lock_irqsave(&events->pmu_lock, flags); |
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val = armv6_pmcr_read(); |
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val |= ARMV6_PMCR_ENABLE; |
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armv6_pmcr_write(val); |
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
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} |
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static void armv6pmu_stop(struct arm_pmu *cpu_pmu) |
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{ |
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unsigned long flags, val; |
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
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raw_spin_lock_irqsave(&events->pmu_lock, flags); |
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val = armv6_pmcr_read(); |
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val &= ~ARMV6_PMCR_ENABLE; |
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armv6_pmcr_write(val); |
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raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
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} |
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static int |
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armv6pmu_get_event_idx(struct pmu_hw_events *cpuc, |
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struct perf_event *event) |
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{ |
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struct hw_perf_event *hwc = &event->hw; |
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/* Always place a cycle counter into the cycle counter. */ |
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if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) { |
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if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask)) |
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return -EAGAIN; |
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return ARMV6_CYCLE_COUNTER; |
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} else { |
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/* |
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* For anything other than a cycle counter, try and use |
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* counter0 and counter1. |
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*/ |
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if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) |
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return ARMV6_COUNTER1; |
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if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) |
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return ARMV6_COUNTER0; |
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/* The counters are all in use. */ |
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return -EAGAIN; |
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} |
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} |
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static void armv6pmu_clear_event_idx(struct pmu_hw_events *cpuc, |
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struct perf_event *event) |
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{ |
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clear_bit(event->hw.idx, cpuc->used_mask); |
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} |
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static void armv6pmu_disable_event(struct perf_event *event) |
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{ |
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unsigned long val, mask, evt, flags; |
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struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
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struct hw_perf_event *hwc = &event->hw; |
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struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
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int idx = hwc->idx; |
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|
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if (ARMV6_CYCLE_COUNTER == idx) { |
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mask = ARMV6_PMCR_CCOUNT_IEN; |
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evt = 0; |
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} else if (ARMV6_COUNTER0 == idx) { |
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mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK; |
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evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT; |
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} else if (ARMV6_COUNTER1 == idx) { |
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mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK; |
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evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT; |
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} else { |
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WARN_ONCE(1, "invalid counter number (%d)\n", idx); |
|
return; |
|
} |
|
|
|
/* |
|
* Mask out the current event and set the counter to count the number |
|
* of ETM bus signal assertion cycles. The external reporting should |
|
* be disabled and so this should never increment. |
|
*/ |
|
raw_spin_lock_irqsave(&events->pmu_lock, flags); |
|
val = armv6_pmcr_read(); |
|
val &= ~mask; |
|
val |= evt; |
|
armv6_pmcr_write(val); |
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
|
} |
|
|
|
static void armv6mpcore_pmu_disable_event(struct perf_event *event) |
|
{ |
|
unsigned long val, mask, flags, evt = 0; |
|
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
|
struct hw_perf_event *hwc = &event->hw; |
|
struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
|
int idx = hwc->idx; |
|
|
|
if (ARMV6_CYCLE_COUNTER == idx) { |
|
mask = ARMV6_PMCR_CCOUNT_IEN; |
|
} else if (ARMV6_COUNTER0 == idx) { |
|
mask = ARMV6_PMCR_COUNT0_IEN; |
|
} else if (ARMV6_COUNTER1 == idx) { |
|
mask = ARMV6_PMCR_COUNT1_IEN; |
|
} else { |
|
WARN_ONCE(1, "invalid counter number (%d)\n", idx); |
|
return; |
|
} |
|
|
|
/* |
|
* Unlike UP ARMv6, we don't have a way of stopping the counters. We |
|
* simply disable the interrupt reporting. |
|
*/ |
|
raw_spin_lock_irqsave(&events->pmu_lock, flags); |
|
val = armv6_pmcr_read(); |
|
val &= ~mask; |
|
val |= evt; |
|
armv6_pmcr_write(val); |
|
raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
|
} |
|
|
|
static int armv6_map_event(struct perf_event *event) |
|
{ |
|
return armpmu_map_event(event, &armv6_perf_map, |
|
&armv6_perf_cache_map, 0xFF); |
|
} |
|
|
|
static void armv6pmu_init(struct arm_pmu *cpu_pmu) |
|
{ |
|
cpu_pmu->handle_irq = armv6pmu_handle_irq; |
|
cpu_pmu->enable = armv6pmu_enable_event; |
|
cpu_pmu->disable = armv6pmu_disable_event; |
|
cpu_pmu->read_counter = armv6pmu_read_counter; |
|
cpu_pmu->write_counter = armv6pmu_write_counter; |
|
cpu_pmu->get_event_idx = armv6pmu_get_event_idx; |
|
cpu_pmu->clear_event_idx = armv6pmu_clear_event_idx; |
|
cpu_pmu->start = armv6pmu_start; |
|
cpu_pmu->stop = armv6pmu_stop; |
|
cpu_pmu->map_event = armv6_map_event; |
|
cpu_pmu->num_events = 3; |
|
} |
|
|
|
static int armv6_1136_pmu_init(struct arm_pmu *cpu_pmu) |
|
{ |
|
armv6pmu_init(cpu_pmu); |
|
cpu_pmu->name = "armv6_1136"; |
|
return 0; |
|
} |
|
|
|
static int armv6_1156_pmu_init(struct arm_pmu *cpu_pmu) |
|
{ |
|
armv6pmu_init(cpu_pmu); |
|
cpu_pmu->name = "armv6_1156"; |
|
return 0; |
|
} |
|
|
|
static int armv6_1176_pmu_init(struct arm_pmu *cpu_pmu) |
|
{ |
|
armv6pmu_init(cpu_pmu); |
|
cpu_pmu->name = "armv6_1176"; |
|
return 0; |
|
} |
|
|
|
/* |
|
* ARMv6mpcore is almost identical to single core ARMv6 with the exception |
|
* that some of the events have different enumerations and that there is no |
|
* *hack* to stop the programmable counters. To stop the counters we simply |
|
* disable the interrupt reporting and update the event. When unthrottling we |
|
* reset the period and enable the interrupt reporting. |
|
*/ |
|
|
|
static int armv6mpcore_map_event(struct perf_event *event) |
|
{ |
|
return armpmu_map_event(event, &armv6mpcore_perf_map, |
|
&armv6mpcore_perf_cache_map, 0xFF); |
|
} |
|
|
|
static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu) |
|
{ |
|
cpu_pmu->name = "armv6_11mpcore"; |
|
cpu_pmu->handle_irq = armv6pmu_handle_irq; |
|
cpu_pmu->enable = armv6pmu_enable_event; |
|
cpu_pmu->disable = armv6mpcore_pmu_disable_event; |
|
cpu_pmu->read_counter = armv6pmu_read_counter; |
|
cpu_pmu->write_counter = armv6pmu_write_counter; |
|
cpu_pmu->get_event_idx = armv6pmu_get_event_idx; |
|
cpu_pmu->clear_event_idx = armv6pmu_clear_event_idx; |
|
cpu_pmu->start = armv6pmu_start; |
|
cpu_pmu->stop = armv6pmu_stop; |
|
cpu_pmu->map_event = armv6mpcore_map_event; |
|
cpu_pmu->num_events = 3; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id armv6_pmu_of_device_ids[] = { |
|
{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, |
|
{.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init}, |
|
{.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init}, |
|
{ /* sentinel value */ } |
|
}; |
|
|
|
static const struct pmu_probe_info armv6_pmu_probe_table[] = { |
|
ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init), |
|
ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init), |
|
ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init), |
|
ARM_PMU_PROBE(ARM_CPU_PART_ARM11MPCORE, armv6mpcore_pmu_init), |
|
{ /* sentinel value */ } |
|
}; |
|
|
|
static int armv6_pmu_device_probe(struct platform_device *pdev) |
|
{ |
|
return arm_pmu_device_probe(pdev, armv6_pmu_of_device_ids, |
|
armv6_pmu_probe_table); |
|
} |
|
|
|
static struct platform_driver armv6_pmu_driver = { |
|
.driver = { |
|
.name = "armv6-pmu", |
|
.of_match_table = armv6_pmu_of_device_ids, |
|
}, |
|
.probe = armv6_pmu_device_probe, |
|
}; |
|
|
|
builtin_platform_driver(armv6_pmu_driver); |
|
#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */
|
|
|