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615 lines
19 KiB
615 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ALPHA_T2__H__ |
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#define __ALPHA_T2__H__ |
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/* Fit everything into one 128MB HAE window. */ |
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#define T2_ONE_HAE_WINDOW 1 |
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#include <linux/types.h> |
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#include <linux/spinlock.h> |
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#include <asm/compiler.h> |
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/* |
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* T2 is the internal name for the core logic chipset which provides |
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* memory controller and PCI access for the SABLE-based systems. |
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* |
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* This file is based on: |
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* |
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* SABLE I/O Specification |
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* Revision/Update Information: 1.3 |
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* |
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* [email protected] Initial Version. |
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* |
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*/ |
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#define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */ |
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/* GAMMA-SABLE is a SABLE with EV5-based CPUs */ |
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/* All LYNX machines, EV4 or EV5, use the GAMMA bias also */ |
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#define _GAMMA_BIAS 0x8000000000UL |
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#if defined(CONFIG_ALPHA_GENERIC) |
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#define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias |
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#elif defined(CONFIG_ALPHA_GAMMA) |
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#define GAMMA_BIAS _GAMMA_BIAS |
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#else |
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#define GAMMA_BIAS 0 |
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#endif |
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/* |
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* Memory spaces: |
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*/ |
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#define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL) |
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#define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL) |
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#define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL) |
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#define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL) |
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#define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL) |
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#define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL) |
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#define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL) |
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#define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL) |
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#define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL) |
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#define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL) |
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#define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL) |
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#define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL) |
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#define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL) |
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#define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL) |
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#define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL) |
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#define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL) |
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#define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL) |
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#define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL) |
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#define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL) |
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#define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL) |
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#define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL) |
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#define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL) |
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#define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL) |
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#define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL) |
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/* The CSRs below are T3/T4 only */ |
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#define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL) |
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#define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL) |
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#define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL) |
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#define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL) |
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#define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL) |
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#define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL) |
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#define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL) |
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#define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL) |
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#define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL) |
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#define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL) |
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#define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL) |
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#define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL) |
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#define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL) |
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#define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL) |
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#define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL) |
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#define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL) |
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#define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL) |
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#define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL) |
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#ifndef T2_ONE_HAE_WINDOW |
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#define T2_HAE_ADDRESS T2_HAE_1 |
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#endif |
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/* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to |
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3.8fff.ffff |
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* |
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* +--------------+ 3 8000 0000 |
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* | CPU 0 CSRs | |
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* +--------------+ 3 8100 0000 |
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* | CPU 1 CSRs | |
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* +--------------+ 3 8200 0000 |
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* | CPU 2 CSRs | |
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* +--------------+ 3 8300 0000 |
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* | CPU 3 CSRs | |
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* +--------------+ 3 8400 0000 |
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* | CPU Reserved | |
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* +--------------+ 3 8700 0000 |
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* | Mem Reserved | |
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* +--------------+ 3 8800 0000 |
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* | Mem 0 CSRs | |
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* +--------------+ 3 8900 0000 |
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* | Mem 1 CSRs | |
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* +--------------+ 3 8a00 0000 |
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* | Mem 2 CSRs | |
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* +--------------+ 3 8b00 0000 |
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* | Mem 3 CSRs | |
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* +--------------+ 3 8c00 0000 |
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* | Mem Reserved | |
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* +--------------+ 3 8e00 0000 |
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* | PCI Bridge | |
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* +--------------+ 3 8f00 0000 |
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* | Expansion IO | |
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* +--------------+ 3 9000 0000 |
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* |
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* |
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*/ |
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#define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L) |
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#define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L) |
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#define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L) |
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#define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L) |
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#define T2_CPUn_BASE(n) (T2_CPU0_BASE + (((n)&3) * 0x001000000L)) |
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#define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L) |
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#define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L) |
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#define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L) |
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#define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L) |
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/* |
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* Sable CPU Module CSRS |
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* |
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* These are CSRs for hardware other than the CPU chip on the CPU module. |
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* The CPU module has Backup Cache control logic, Cbus control logic, and |
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* interrupt control logic on it. There is a duplicate tag store to speed |
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* up maintaining cache coherency. |
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*/ |
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struct sable_cpu_csr { |
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unsigned long bcc; long fill_00[3]; /* Backup Cache Control */ |
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unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */ |
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unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */ |
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unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */ |
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unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */ |
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unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */ |
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unsigned long cbctl; long fill_06[3]; /* CBus Control */ |
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unsigned long cbe; long fill_07[3]; /* CBus Error */ |
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unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */ |
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unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */ |
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unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */ |
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unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */ |
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unsigned long sic; long fill_12[3]; /* System Interrupt Clear */ |
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unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */ |
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unsigned long madrl; long fill_14[3]; /* CBus Miss Address */ |
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unsigned long rev; long fill_15[3]; /* CMIC Revision */ |
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}; |
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/* |
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* Data structure for handling T2 machine checks: |
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*/ |
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struct el_t2_frame_header { |
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unsigned int elcf_fid; /* Frame ID (from above) */ |
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unsigned int elcf_size; /* Size of frame in bytes */ |
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}; |
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struct el_t2_procdata_mcheck { |
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unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */ |
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/* EV4-specific fields */ |
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unsigned long elfmc_exc_addr; /* Addr of excepting insn. */ |
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unsigned long elfmc_exc_sum; /* Summary of arith traps. */ |
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unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */ |
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unsigned long elfmc_iccsr; /* IBox hardware enables. */ |
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unsigned long elfmc_pal_base; /* Base address for PALcode. */ |
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unsigned long elfmc_hier; /* Hardware Interrupt Enable. */ |
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unsigned long elfmc_hirr; /* Hardware Interrupt Request. */ |
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unsigned long elfmc_mm_csr; /* D-stream fault info. */ |
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unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */ |
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unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ |
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unsigned long elfmc_abox_ctl; /* ABox Control Register. */ |
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unsigned long elfmc_biu_stat; /* BIU Status. */ |
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unsigned long elfmc_biu_addr; /* BUI Address. */ |
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unsigned long elfmc_biu_ctl; /* BIU Control. */ |
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unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */ |
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unsigned long elfmc_fill_addr;/* Cache block which was being read. */ |
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unsigned long elfmc_va; /* Effective VA of fault or miss. */ |
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unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */ |
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}; |
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/* |
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* Sable processor specific Machine Check Data segment. |
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*/ |
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struct el_t2_logout_header { |
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unsigned int elfl_size; /* size in bytes of logout area. */ |
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unsigned int elfl_sbz1:31; /* Should be zero. */ |
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unsigned int elfl_retry:1; /* Retry flag. */ |
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unsigned int elfl_procoffset; /* Processor-specific offset. */ |
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unsigned int elfl_sysoffset; /* Offset of system-specific. */ |
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unsigned int elfl_error_type; /* PAL error type code. */ |
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unsigned int elfl_frame_rev; /* PAL Frame revision. */ |
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}; |
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struct el_t2_sysdata_mcheck { |
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unsigned long elcmc_bcc; /* CSR 0 */ |
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unsigned long elcmc_bcce; /* CSR 1 */ |
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unsigned long elcmc_bccea; /* CSR 2 */ |
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unsigned long elcmc_bcue; /* CSR 3 */ |
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unsigned long elcmc_bcuea; /* CSR 4 */ |
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unsigned long elcmc_dter; /* CSR 5 */ |
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unsigned long elcmc_cbctl; /* CSR 6 */ |
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unsigned long elcmc_cbe; /* CSR 7 */ |
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unsigned long elcmc_cbeal; /* CSR 8 */ |
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unsigned long elcmc_cbeah; /* CSR 9 */ |
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unsigned long elcmc_pmbx; /* CSR 10 */ |
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unsigned long elcmc_ipir; /* CSR 11 */ |
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unsigned long elcmc_sic; /* CSR 12 */ |
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unsigned long elcmc_adlk; /* CSR 13 */ |
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unsigned long elcmc_madrl; /* CSR 14 */ |
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unsigned long elcmc_crrev4; /* CSR 15 */ |
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}; |
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/* |
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* Sable memory error frame - sable pfms section 3.42 |
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*/ |
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struct el_t2_data_memory { |
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struct el_t2_frame_header elcm_hdr; /* ID$MEM-FERR = 0x08 */ |
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unsigned int elcm_module; /* Module id. */ |
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unsigned int elcm_res04; /* Reserved. */ |
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unsigned long elcm_merr; /* CSR0: Error Reg 1. */ |
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unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */ |
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unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */ |
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unsigned long elcm_mconf; /* CSR3: Configuration. */ |
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unsigned long elcm_medc1; /* CSR4: EDC Status 1. */ |
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unsigned long elcm_medc2; /* CSR5: EDC Status 2. */ |
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unsigned long elcm_medcc; /* CSR6: EDC Control. */ |
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unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */ |
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unsigned long elcm_mref; /* CSR8: Refresh Control. */ |
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unsigned long elcm_filter; /* CSR9: CRD Filter Control. */ |
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}; |
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/* |
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* Sable other CPU error frame - sable pfms section 3.43 |
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*/ |
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struct el_t2_data_other_cpu { |
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short elco_cpuid; /* CPU ID */ |
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short elco_res02[3]; |
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unsigned long elco_bcc; /* CSR 0 */ |
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unsigned long elco_bcce; /* CSR 1 */ |
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unsigned long elco_bccea; /* CSR 2 */ |
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unsigned long elco_bcue; /* CSR 3 */ |
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unsigned long elco_bcuea; /* CSR 4 */ |
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unsigned long elco_dter; /* CSR 5 */ |
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unsigned long elco_cbctl; /* CSR 6 */ |
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unsigned long elco_cbe; /* CSR 7 */ |
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unsigned long elco_cbeal; /* CSR 8 */ |
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unsigned long elco_cbeah; /* CSR 9 */ |
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unsigned long elco_pmbx; /* CSR 10 */ |
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unsigned long elco_ipir; /* CSR 11 */ |
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unsigned long elco_sic; /* CSR 12 */ |
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unsigned long elco_adlk; /* CSR 13 */ |
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unsigned long elco_madrl; /* CSR 14 */ |
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unsigned long elco_crrev4; /* CSR 15 */ |
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}; |
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/* |
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* Sable other CPU error frame - sable pfms section 3.44 |
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*/ |
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struct el_t2_data_t2{ |
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struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */ |
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unsigned long elct_iocsr; /* IO Control and Status Register */ |
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unsigned long elct_cerr1; /* Cbus Error Register 1 */ |
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unsigned long elct_cerr2; /* Cbus Error Register 2 */ |
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unsigned long elct_cerr3; /* Cbus Error Register 3 */ |
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unsigned long elct_perr1; /* PCI Error Register 1 */ |
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unsigned long elct_perr2; /* PCI Error Register 2 */ |
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unsigned long elct_hae0_1; /* High Address Extension Register 1 */ |
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unsigned long elct_hae0_2; /* High Address Extension Register 2 */ |
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unsigned long elct_hbase; /* High Base Register */ |
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unsigned long elct_wbase1; /* Window Base Register 1 */ |
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unsigned long elct_wmask1; /* Window Mask Register 1 */ |
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unsigned long elct_tbase1; /* Translated Base Register 1 */ |
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unsigned long elct_wbase2; /* Window Base Register 2 */ |
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unsigned long elct_wmask2; /* Window Mask Register 2 */ |
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unsigned long elct_tbase2; /* Translated Base Register 2 */ |
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unsigned long elct_tdr0; /* TLB Data Register 0 */ |
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unsigned long elct_tdr1; /* TLB Data Register 1 */ |
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unsigned long elct_tdr2; /* TLB Data Register 2 */ |
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unsigned long elct_tdr3; /* TLB Data Register 3 */ |
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unsigned long elct_tdr4; /* TLB Data Register 4 */ |
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unsigned long elct_tdr5; /* TLB Data Register 5 */ |
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unsigned long elct_tdr6; /* TLB Data Register 6 */ |
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unsigned long elct_tdr7; /* TLB Data Register 7 */ |
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}; |
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/* |
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* Sable error log data structure - sable pfms section 3.40 |
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*/ |
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struct el_t2_data_corrected { |
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unsigned long elcpb_biu_stat; |
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unsigned long elcpb_biu_addr; |
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unsigned long elcpb_biu_ctl; |
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unsigned long elcpb_fill_syndrome; |
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unsigned long elcpb_fill_addr; |
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unsigned long elcpb_bc_tag; |
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}; |
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/* |
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* Sable error log data structure |
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* Note there are 4 memory slots on sable (see t2.h) |
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*/ |
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struct el_t2_frame_mcheck { |
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struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */ |
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struct el_t2_logout_header elfmc_hdr; |
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struct el_t2_procdata_mcheck elfmc_procdata; |
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struct el_t2_sysdata_mcheck elfmc_sysdata; |
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struct el_t2_data_t2 elfmc_t2data; |
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struct el_t2_data_memory elfmc_memdata[4]; |
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struct el_t2_frame_header elfmc_footer; /* empty */ |
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}; |
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/* |
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* Sable error log data structures on memory errors |
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*/ |
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struct el_t2_frame_corrected { |
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struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */ |
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struct el_t2_logout_header elfcc_hdr; |
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struct el_t2_data_corrected elfcc_procdata; |
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/* struct el_t2_data_t2 elfcc_t2data; */ |
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/* struct el_t2_data_memory elfcc_memdata[4]; */ |
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struct el_t2_frame_header elfcc_footer; /* empty */ |
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}; |
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#ifdef __KERNEL__ |
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#ifndef __EXTERN_INLINE |
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#define __EXTERN_INLINE extern inline |
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#define __IO_EXTERN_INLINE |
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#endif |
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/* |
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* I/O functions: |
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* |
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* T2 (the core logic PCI/memory support chipset for the SABLE |
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* series of processors uses a sparse address mapping scheme to |
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* get at PCI memory and I/O. |
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*/ |
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#define vip volatile int * |
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#define vuip volatile unsigned int * |
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extern inline u8 t2_inb(unsigned long addr) |
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{ |
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long result = *(vip) ((addr << 5) + T2_IO + 0x00); |
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return __kernel_extbl(result, addr & 3); |
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} |
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extern inline void t2_outb(u8 b, unsigned long addr) |
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{ |
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unsigned long w; |
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w = __kernel_insbl(b, addr & 3); |
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*(vuip) ((addr << 5) + T2_IO + 0x00) = w; |
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mb(); |
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} |
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extern inline u16 t2_inw(unsigned long addr) |
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{ |
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long result = *(vip) ((addr << 5) + T2_IO + 0x08); |
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return __kernel_extwl(result, addr & 3); |
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} |
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extern inline void t2_outw(u16 b, unsigned long addr) |
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{ |
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unsigned long w; |
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w = __kernel_inswl(b, addr & 3); |
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*(vuip) ((addr << 5) + T2_IO + 0x08) = w; |
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mb(); |
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} |
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extern inline u32 t2_inl(unsigned long addr) |
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{ |
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return *(vuip) ((addr << 5) + T2_IO + 0x18); |
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} |
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extern inline void t2_outl(u32 b, unsigned long addr) |
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{ |
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*(vuip) ((addr << 5) + T2_IO + 0x18) = b; |
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mb(); |
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} |
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/* |
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* Memory functions. |
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* |
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* For reading and writing 8 and 16 bit quantities we need to |
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* go through one of the three sparse address mapping regions |
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* and use the HAE_MEM CSR to provide some bits of the address. |
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* The following few routines use only sparse address region 1 |
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* which gives 1Gbyte of accessible space which relates exactly |
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* to the amount of PCI memory mapping *into* system address space. |
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* See p 6-17 of the specification but it looks something like this: |
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* |
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* 21164 Address: |
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* |
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* 3 2 1 |
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* 9876543210987654321098765432109876543210 |
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* 1ZZZZ0.PCI.QW.Address............BBLL |
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* |
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* ZZ = SBZ |
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* BB = Byte offset |
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* LL = Transfer length |
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* |
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* PCI Address: |
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* |
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* 3 2 1 |
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* 10987654321098765432109876543210 |
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* HHH....PCI.QW.Address........ 00 |
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* |
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* HHH = 31:29 HAE_MEM CSR |
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* |
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*/ |
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#ifdef T2_ONE_HAE_WINDOW |
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#define t2_set_hae |
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#else |
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#define t2_set_hae { \ |
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unsigned long msb = addr >> 27; \ |
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addr &= T2_MEM_R1_MASK; \ |
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set_hae(msb); \ |
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} |
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#endif |
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/* |
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* NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since |
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* they may be called directly, rather than through the |
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* ioreadNN/iowriteNN routines. |
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*/ |
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__EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
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unsigned long result; |
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t2_set_hae; |
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result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00); |
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return __kernel_extbl(result, addr & 3); |
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} |
|
|
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__EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr) |
|
{ |
|
unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
|
unsigned long result; |
|
|
|
t2_set_hae; |
|
|
|
result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); |
|
return __kernel_extwl(result, addr & 3); |
|
} |
|
|
|
/* |
|
* On SABLE with T2, we must use SPARSE memory even for 32-bit access, |
|
* because we cannot access all of DENSE without changing its HAE. |
|
*/ |
|
__EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr) |
|
{ |
|
unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
|
unsigned long result; |
|
|
|
t2_set_hae; |
|
|
|
result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); |
|
return result & 0xffffffffUL; |
|
} |
|
|
|
__EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr) |
|
{ |
|
unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
|
unsigned long r0, r1, work; |
|
|
|
t2_set_hae; |
|
|
|
work = (addr << 5) + T2_SPARSE_MEM + 0x18; |
|
r0 = *(vuip)(work); |
|
r1 = *(vuip)(work + (4 << 5)); |
|
return r1 << 32 | r0; |
|
} |
|
|
|
__EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr) |
|
{ |
|
unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
|
unsigned long w; |
|
|
|
t2_set_hae; |
|
|
|
w = __kernel_insbl(b, addr & 3); |
|
*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; |
|
} |
|
|
|
__EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr) |
|
{ |
|
unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
|
unsigned long w; |
|
|
|
t2_set_hae; |
|
|
|
w = __kernel_inswl(b, addr & 3); |
|
*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w; |
|
} |
|
|
|
/* |
|
* On SABLE with T2, we must use SPARSE memory even for 32-bit access, |
|
* because we cannot access all of DENSE without changing its HAE. |
|
*/ |
|
__EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr) |
|
{ |
|
unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
|
|
|
t2_set_hae; |
|
|
|
*(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b; |
|
} |
|
|
|
__EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr) |
|
{ |
|
unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; |
|
unsigned long work; |
|
|
|
t2_set_hae; |
|
|
|
work = (addr << 5) + T2_SPARSE_MEM + 0x18; |
|
*(vuip)work = b; |
|
*(vuip)(work + (4 << 5)) = b >> 32; |
|
} |
|
|
|
__EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr) |
|
{ |
|
return (void __iomem *)(addr + T2_IO); |
|
} |
|
|
|
__EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr, |
|
unsigned long size) |
|
{ |
|
return (void __iomem *)(addr + T2_DENSE_MEM); |
|
} |
|
|
|
__EXTERN_INLINE int t2_is_ioaddr(unsigned long addr) |
|
{ |
|
return (long)addr >= 0; |
|
} |
|
|
|
__EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr) |
|
{ |
|
return (unsigned long)addr >= T2_DENSE_MEM; |
|
} |
|
|
|
/* New-style ioread interface. The mmio routines are so ugly for T2 that |
|
it doesn't make sense to merge the pio and mmio routines. */ |
|
|
|
#define IOPORT(OS, NS) \ |
|
__EXTERN_INLINE unsigned int t2_ioread##NS(const void __iomem *xaddr) \ |
|
{ \ |
|
if (t2_is_mmio(xaddr)) \ |
|
return t2_read##OS(xaddr); \ |
|
else \ |
|
return t2_in##OS((unsigned long)xaddr - T2_IO); \ |
|
} \ |
|
__EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \ |
|
{ \ |
|
if (t2_is_mmio(xaddr)) \ |
|
t2_write##OS(b, xaddr); \ |
|
else \ |
|
t2_out##OS(b, (unsigned long)xaddr - T2_IO); \ |
|
} |
|
|
|
IOPORT(b, 8) |
|
IOPORT(w, 16) |
|
IOPORT(l, 32) |
|
|
|
#undef IOPORT |
|
|
|
#undef vip |
|
#undef vuip |
|
|
|
#undef __IO_PREFIX |
|
#define __IO_PREFIX t2 |
|
#define t2_trivial_rw_bw 0 |
|
#define t2_trivial_rw_lq 0 |
|
#define t2_trivial_io_bw 0 |
|
#define t2_trivial_io_lq 0 |
|
#define t2_trivial_iounmap 1 |
|
#include <asm/io_trivial.h> |
|
|
|
#ifdef __IO_EXTERN_INLINE |
|
#undef __EXTERN_INLINE |
|
#undef __IO_EXTERN_INLINE |
|
#endif |
|
|
|
#endif /* __KERNEL__ */ |
|
|
|
#endif /* __ALPHA_T2__H__ */
|
|
|