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382 lines
12 KiB
382 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ALPHA_MCPCIA__H__ |
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#define __ALPHA_MCPCIA__H__ |
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/* Define to experiment with fitting everything into one 128MB HAE window. |
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One window per bus, that is. */ |
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#define MCPCIA_ONE_HAE_WINDOW 1 |
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#include <linux/types.h> |
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#include <asm/compiler.h> |
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#include <asm/mce.h> |
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/* |
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* MCPCIA is the internal name for a core logic chipset which provides |
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* PCI access for the RAWHIDE family of systems. |
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* |
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* This file is based on: |
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* |
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* RAWHIDE System Programmer's Manual |
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* 16-May-96 |
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* Rev. 1.4 |
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* |
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*/ |
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/*------------------------------------------------------------------------** |
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** ** |
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** I/O procedures ** |
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** ** |
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** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers ** |
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** inportbxt: 8 bits only ** |
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** inport: alias of inportw ** |
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** outport: alias of outportw ** |
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** ** |
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** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers ** |
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** inmembxt: 8 bits only ** |
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** inmem: alias of inmemw ** |
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** outmem: alias of outmemw ** |
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** ** |
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**------------------------------------------------------------------------*/ |
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/* MCPCIA ADDRESS BIT DEFINITIONS |
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* |
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* 3333 3333 3322 2222 2222 1111 1111 11 |
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* 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 |
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* ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- |
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* 1 000 |
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* ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- |
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* | |\| |
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* | Byte Enable --+ | |
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* | Transfer Length --+ |
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* +-- IO space, not cached |
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* |
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* Byte Transfer |
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* Enable Length Transfer Byte Address |
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* adr<6:5> adr<4:3> Length Enable Adder |
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* --------------------------------------------- |
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* 00 00 Byte 1110 0x000 |
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* 01 00 Byte 1101 0x020 |
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* 10 00 Byte 1011 0x040 |
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* 11 00 Byte 0111 0x060 |
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* |
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* 00 01 Word 1100 0x008 |
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* 01 01 Word 1001 0x028 <= Not supported in this code. |
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* 10 01 Word 0011 0x048 |
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* |
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* 00 10 Tribyte 1000 0x010 |
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* 01 10 Tribyte 0001 0x030 |
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* |
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* 10 11 Longword 0000 0x058 |
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* |
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* Note that byte enables are asserted low. |
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* |
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*/ |
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#define MCPCIA_MAX_HOSES 4 |
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#define MCPCIA_MID(m) ((unsigned long)(m) << 33) |
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/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. |
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Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */ |
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#define MCPCIA_HOSE2MID(h) ((h) + 4) |
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#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */ |
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/* |
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* Memory spaces: |
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*/ |
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#define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m)) |
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#define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m)) |
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#define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m)) |
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#define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m)) |
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#define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m)) |
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#define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m)) |
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#define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m)) |
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#define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m)) |
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/* |
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* General Registers |
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*/ |
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#define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000) |
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#define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040) |
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#define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080) |
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#define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100) |
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#define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400) |
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#define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440) |
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#define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480) |
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#define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0) |
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/* |
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* Interrupt Control registers |
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*/ |
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#define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500) |
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#define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540) |
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#define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580) |
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#define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0) |
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#define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600) |
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#define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640) |
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#define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680) |
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#define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00) |
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#define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40) |
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/* |
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* Performance Monitor registers |
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*/ |
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#define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300) |
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#define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340) |
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/* |
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* Diagnostic Registers |
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*/ |
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#define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700) |
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#define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0) |
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/* |
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* Error registers |
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*/ |
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#define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800) |
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#define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840) |
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#define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880) |
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#define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040) |
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#define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000) |
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#define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040) |
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#define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080) |
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#define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000) |
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#define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040) |
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#define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080) |
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/* |
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* PCI Address Translation Registers. |
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*/ |
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#define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300) |
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#define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340) |
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#define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400) |
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#define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440) |
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#define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480) |
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#define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500) |
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#define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540) |
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#define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580) |
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#define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600) |
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#define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640) |
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#define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680) |
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#define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700) |
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#define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740) |
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#define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780) |
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/* Hack! Only words for bus 0. */ |
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#ifndef MCPCIA_ONE_HAE_WINDOW |
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#define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4) |
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#endif |
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#define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4) |
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/* |
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* The canonical non-remaped I/O and MEM addresses have these values |
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* subtracted out. This is arranged so that folks manipulating ISA |
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* devices can use their familiar numbers and have them map to bus 0. |
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*/ |
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#define MCPCIA_IO_BIAS MCPCIA_IO(4) |
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#define MCPCIA_MEM_BIAS MCPCIA_DENSE(4) |
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/* Offset between ram physical addresses and pci64 DAC bus addresses. */ |
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#define MCPCIA_DAC_OFFSET (1UL << 40) |
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/* |
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* Data structure for handling MCPCIA machine checks: |
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*/ |
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struct el_MCPCIA_uncorrected_frame_mcheck { |
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struct el_common header; |
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struct el_common_EV5_uncorrectable_mcheck procdata; |
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}; |
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#ifdef __KERNEL__ |
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#ifndef __EXTERN_INLINE |
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#define __EXTERN_INLINE extern inline |
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#define __IO_EXTERN_INLINE |
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#endif |
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/* |
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* I/O functions: |
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* |
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* MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164) |
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* and EV56 (21164a) processors, can use either a sparse address mapping |
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* scheme, or the so-called byte-word PCI address space, to get at PCI memory |
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* and I/O. |
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* |
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* Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE. |
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*/ |
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/* |
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* Memory functions. 64-bit and 32-bit accesses are done through |
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* dense memory space, everything else through sparse space. |
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* |
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* For reading and writing 8 and 16 bit quantities we need to |
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* go through one of the three sparse address mapping regions |
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* and use the HAE_MEM CSR to provide some bits of the address. |
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* The following few routines use only sparse address region 1 |
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* which gives 1Gbyte of accessible space which relates exactly |
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* to the amount of PCI memory mapping *into* system address space. |
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* See p 6-17 of the specification but it looks something like this: |
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* |
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* 21164 Address: |
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* |
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* 3 2 1 |
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* 9876543210987654321098765432109876543210 |
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* 1ZZZZ0.PCI.QW.Address............BBLL |
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* |
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* ZZ = SBZ |
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* BB = Byte offset |
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* LL = Transfer length |
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* |
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* PCI Address: |
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* |
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* 3 2 1 |
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* 10987654321098765432109876543210 |
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* HHH....PCI.QW.Address........ 00 |
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* |
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* HHH = 31:29 HAE_MEM CSR |
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* |
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*/ |
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#define vip volatile int __force * |
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#define vuip volatile unsigned int __force * |
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#ifndef MCPCIA_ONE_HAE_WINDOW |
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#define MCPCIA_FROB_MMIO \ |
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if (__mcpcia_is_mmio(hose)) { \ |
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set_hae(hose & 0xffffffff); \ |
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hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \ |
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} |
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#else |
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#define MCPCIA_FROB_MMIO \ |
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if (__mcpcia_is_mmio(hose)) { \ |
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hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \ |
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} |
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#endif |
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extern inline int __mcpcia_is_mmio(unsigned long addr) |
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{ |
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return (addr & 0x80000000UL) == 0; |
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} |
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__EXTERN_INLINE unsigned int mcpcia_ioread8(const void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
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unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
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unsigned long result; |
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MCPCIA_FROB_MMIO; |
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result = *(vip) ((addr << 5) + hose + 0x00); |
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return __kernel_extbl(result, addr & 3); |
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} |
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__EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
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unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
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unsigned long w; |
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MCPCIA_FROB_MMIO; |
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w = __kernel_insbl(b, addr & 3); |
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*(vuip) ((addr << 5) + hose + 0x00) = w; |
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} |
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__EXTERN_INLINE unsigned int mcpcia_ioread16(const void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
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unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
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unsigned long result; |
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MCPCIA_FROB_MMIO; |
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result = *(vip) ((addr << 5) + hose + 0x08); |
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return __kernel_extwl(result, addr & 3); |
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} |
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__EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK; |
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unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK; |
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unsigned long w; |
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MCPCIA_FROB_MMIO; |
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w = __kernel_inswl(b, addr & 3); |
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*(vuip) ((addr << 5) + hose + 0x08) = w; |
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} |
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__EXTERN_INLINE unsigned int mcpcia_ioread32(const void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long)xaddr; |
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if (!__mcpcia_is_mmio(addr)) |
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addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18; |
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return *(vuip)addr; |
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} |
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__EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long)xaddr; |
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if (!__mcpcia_is_mmio(addr)) |
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addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18; |
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*(vuip)addr = b; |
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} |
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__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr) |
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{ |
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return (void __iomem *)(addr + MCPCIA_IO_BIAS); |
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} |
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__EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr, |
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unsigned long size) |
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{ |
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return (void __iomem *)(addr + MCPCIA_MEM_BIAS); |
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} |
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__EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr) |
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{ |
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return addr >= MCPCIA_SPARSE(0); |
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} |
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__EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long) xaddr; |
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return __mcpcia_is_mmio(addr); |
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} |
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#undef MCPCIA_FROB_MMIO |
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#undef vip |
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#undef vuip |
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#undef __IO_PREFIX |
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#define __IO_PREFIX mcpcia |
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#define mcpcia_trivial_rw_bw 2 |
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#define mcpcia_trivial_rw_lq 1 |
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#define mcpcia_trivial_io_bw 0 |
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#define mcpcia_trivial_io_lq 0 |
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#define mcpcia_trivial_iounmap 1 |
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#include <asm/io_trivial.h> |
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#ifdef __IO_EXTERN_INLINE |
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#undef __EXTERN_INLINE |
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#undef __IO_EXTERN_INLINE |
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#endif |
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#endif /* __KERNEL__ */ |
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#endif /* __ALPHA_MCPCIA__H__ */
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