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378 lines
9.2 KiB
378 lines
9.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Marvel systems use the IO7 I/O chip provides PCI/PCIX/AGP access |
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* |
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* This file is based on: |
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* |
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* Marvel / EV7 System Programmer's Manual |
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* Revision 1.00 |
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* 14 May 2001 |
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*/ |
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#ifndef __ALPHA_MARVEL__H__ |
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#define __ALPHA_MARVEL__H__ |
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#include <linux/types.h> |
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#include <linux/spinlock.h> |
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#include <asm/compiler.h> |
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#define MARVEL_MAX_PIDS 32 /* as long as we rely on 43-bit superpage */ |
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#define MARVEL_IRQ_VEC_PE_SHIFT (10) |
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#define MARVEL_IRQ_VEC_IRQ_MASK ((1 << MARVEL_IRQ_VEC_PE_SHIFT) - 1) |
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#define MARVEL_NR_IRQS \ |
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(16 + (MARVEL_MAX_PIDS * (1 << MARVEL_IRQ_VEC_PE_SHIFT))) |
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/* |
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* EV7 RBOX Registers |
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*/ |
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typedef struct { |
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volatile unsigned long csr __attribute__((aligned(16))); |
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} ev7_csr; |
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typedef struct { |
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ev7_csr RBOX_CFG; /* 0x0000 */ |
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ev7_csr RBOX_NSVC; |
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ev7_csr RBOX_EWVC; |
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ev7_csr RBOX_WHAMI; |
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ev7_csr RBOX_TCTL; /* 0x0040 */ |
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ev7_csr RBOX_INT; |
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ev7_csr RBOX_IMASK; |
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ev7_csr RBOX_IREQ; |
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ev7_csr RBOX_INTQ; /* 0x0080 */ |
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ev7_csr RBOX_INTA; |
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ev7_csr RBOX_IT; |
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ev7_csr RBOX_SCRATCH1; |
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ev7_csr RBOX_SCRATCH2; /* 0x00c0 */ |
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ev7_csr RBOX_L_ERR; |
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} ev7_csrs; |
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/* |
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* EV7 CSR addressing macros |
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*/ |
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#define EV7_MASK40(addr) ((addr) & ((1UL << 41) - 1)) |
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#define EV7_KERN_ADDR(addr) ((void *)(IDENT_ADDR | EV7_MASK40(addr))) |
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#define EV7_PE_MASK 0x1ffUL /* 9 bits ( 256 + mem/io ) */ |
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#define EV7_IPE(pe) ((~((long)(pe)) & EV7_PE_MASK) << 35) |
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#define EV7_CSR_PHYS(pe, off) (EV7_IPE(pe) | (0x7FFCUL << 20) | (off)) |
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#define EV7_CSRS_PHYS(pe) (EV7_CSR_PHYS(pe, 0UL)) |
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#define EV7_CSR_KERN(pe, off) (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off))) |
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#define EV7_CSRS_KERN(pe) (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe))) |
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#define EV7_CSR_OFFSET(name) ((unsigned long)&((ev7_csrs *)NULL)->name.csr) |
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/* |
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* IO7 registers |
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*/ |
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typedef struct { |
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volatile unsigned long csr __attribute__((aligned(64))); |
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} io7_csr; |
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typedef struct { |
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/* I/O Port Control Registers */ |
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io7_csr POx_CTRL; /* 0x0000 */ |
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io7_csr POx_CACHE_CTL; |
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io7_csr POx_TIMER; |
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io7_csr POx_IO_ADR_EXT; |
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io7_csr POx_MEM_ADR_EXT; /* 0x0100 */ |
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io7_csr POx_XCAL_CTRL; |
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io7_csr rsvd1[2]; /* ?? spec doesn't show 0x180 */ |
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io7_csr POx_DM_SOURCE; /* 0x0200 */ |
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io7_csr POx_DM_DEST; |
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io7_csr POx_DM_SIZE; |
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io7_csr POx_DM_CTRL; |
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io7_csr rsvd2[4]; /* 0x0300 */ |
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/* AGP Control Registers -- port 3 only */ |
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io7_csr AGP_CAP_ID; /* 0x0400 */ |
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io7_csr AGP_STAT; |
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io7_csr AGP_CMD; |
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io7_csr rsvd3; |
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/* I/O Port Monitor Registers */ |
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io7_csr POx_MONCTL; /* 0x0500 */ |
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io7_csr POx_CTRA; |
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io7_csr POx_CTRB; |
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io7_csr POx_CTR56; |
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io7_csr POx_SCRATCH; /* 0x0600 */ |
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io7_csr POx_XTRA_A; |
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io7_csr POx_XTRA_TS; |
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io7_csr POx_XTRA_Z; |
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io7_csr rsvd4; /* 0x0700 */ |
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io7_csr POx_THRESHA; |
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io7_csr POx_THRESHB; |
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io7_csr rsvd5[33]; |
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/* System Address Space Window Control Registers */ |
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io7_csr POx_WBASE[4]; /* 0x1000 */ |
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io7_csr POx_WMASK[4]; |
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io7_csr POx_TBASE[4]; |
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io7_csr POx_SG_TBIA; |
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io7_csr POx_MSI_WBASE; |
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io7_csr rsvd6[50]; |
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/* I/O Port Error Registers */ |
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io7_csr POx_ERR_SUM; |
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io7_csr POx_FIRST_ERR; |
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io7_csr POx_MSK_HEI; |
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io7_csr POx_TLB_ERR; |
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io7_csr POx_SPL_COMPLT; |
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io7_csr POx_TRANS_SUM; |
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io7_csr POx_FRC_PCI_ERR; |
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io7_csr POx_MULT_ERR; |
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io7_csr rsvd7[8]; |
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/* I/O Port End of Interrupt Registers */ |
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io7_csr EOI_DAT; |
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io7_csr rsvd8[7]; |
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io7_csr POx_IACK_SPECIAL; |
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io7_csr rsvd9[103]; |
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} io7_ioport_csrs; |
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typedef struct { |
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io7_csr IO_ASIC_REV; /* 0x30.0000 */ |
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io7_csr IO_SYS_REV; |
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io7_csr SER_CHAIN3; |
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io7_csr PO7_RST1; |
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io7_csr PO7_RST2; /* 0x30.0100 */ |
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io7_csr POx_RST[4]; |
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io7_csr IO7_DWNH; |
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io7_csr IO7_MAF; |
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io7_csr IO7_MAF_TO; |
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io7_csr IO7_ACC_CLUMP; /* 0x30.0300 */ |
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io7_csr IO7_PMASK; |
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io7_csr IO7_IOMASK; |
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io7_csr IO7_UPH; |
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io7_csr IO7_UPH_TO; /* 0x30.0400 */ |
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io7_csr RBX_IREQ_OFF; |
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io7_csr RBX_INTA_OFF; |
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io7_csr INT_RTY; |
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io7_csr PO7_MONCTL; /* 0x30.0500 */ |
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io7_csr PO7_CTRA; |
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io7_csr PO7_CTRB; |
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io7_csr PO7_CTR56; |
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io7_csr PO7_SCRATCH; /* 0x30.0600 */ |
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io7_csr PO7_XTRA_A; |
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io7_csr PO7_XTRA_TS; |
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io7_csr PO7_XTRA_Z; |
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io7_csr PO7_PMASK; /* 0x30.0700 */ |
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io7_csr PO7_THRESHA; |
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io7_csr PO7_THRESHB; |
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io7_csr rsvd1[97]; |
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io7_csr PO7_ERROR_SUM; /* 0x30.2000 */ |
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io7_csr PO7_BHOLE_MASK; |
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io7_csr PO7_HEI_MSK; |
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io7_csr PO7_CRD_MSK; |
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io7_csr PO7_UNCRR_SYM; /* 0x30.2100 */ |
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io7_csr PO7_CRRCT_SYM; |
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io7_csr PO7_ERR_PKT[2]; |
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io7_csr PO7_UGBGE_SYM; /* 0x30.2200 */ |
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io7_csr rsbv2[887]; |
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io7_csr PO7_LSI_CTL[128]; /* 0x31.0000 */ |
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io7_csr rsvd3[123]; |
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io7_csr HLT_CTL; /* 0x31.3ec0 */ |
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io7_csr HPI_CTL; /* 0x31.3f00 */ |
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io7_csr CRD_CTL; |
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io7_csr STV_CTL; |
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io7_csr HEI_CTL; |
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io7_csr PO7_MSI_CTL[16]; /* 0x31.4000 */ |
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io7_csr rsvd4[240]; |
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/* |
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* Interrupt Diagnostic / Test |
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*/ |
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struct { |
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io7_csr INT_PND; |
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io7_csr INT_CLR; |
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io7_csr INT_EOI; |
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io7_csr rsvd[29]; |
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} INT_DIAG[4]; |
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io7_csr rsvd5[125]; /* 0x31.a000 */ |
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io7_csr MISC_PND; /* 0x31.b800 */ |
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io7_csr rsvd6[31]; |
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io7_csr MSI_PND[16]; /* 0x31.c000 */ |
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io7_csr rsvd7[16]; |
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io7_csr MSI_CLR[16]; /* 0x31.c800 */ |
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} io7_port7_csrs; |
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/* |
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* IO7 DMA Window Base register (POx_WBASEx) |
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*/ |
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#define wbase_m_ena 0x1 |
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#define wbase_m_sg 0x2 |
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#define wbase_m_dac 0x4 |
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#define wbase_m_addr 0xFFF00000 |
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union IO7_POx_WBASE { |
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struct { |
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unsigned ena : 1; /* <0> */ |
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unsigned sg : 1; /* <1> */ |
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unsigned dac : 1; /* <2> -- window 3 only */ |
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unsigned rsvd1 : 17; |
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unsigned addr : 12; /* <31:20> */ |
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unsigned rsvd2 : 32; |
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} bits; |
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unsigned as_long[2]; |
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unsigned as_quad; |
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}; |
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/* |
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* IO7 IID (Interrupt IDentifier) format |
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* |
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* For level-sensative interrupts, int_num is encoded as: |
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* |
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* bus/port slot/device INTx |
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* <7:5> <4:2> <1:0> |
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*/ |
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union IO7_IID { |
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struct { |
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unsigned int_num : 9; /* <8:0> */ |
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unsigned tpu_mask : 4; /* <12:9> rsvd */ |
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unsigned msi : 1; /* 13 */ |
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unsigned ipe : 10; /* <23:14> */ |
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unsigned long rsvd : 40; |
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} bits; |
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unsigned int as_long[2]; |
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unsigned long as_quad; |
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}; |
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/* |
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* IO7 addressing macros |
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*/ |
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#define IO7_KERN_ADDR(addr) (EV7_KERN_ADDR(addr)) |
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#define IO7_PORT_MASK 0x07UL /* 3 bits of port */ |
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#define IO7_IPE(pe) (EV7_IPE(pe)) |
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#define IO7_IPORT(port) ((~((long)(port)) & IO7_PORT_MASK) << 32) |
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#define IO7_HOSE(pe, port) (IO7_IPE(pe) | IO7_IPORT(port)) |
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#define IO7_MEM_PHYS(pe, port) (IO7_HOSE(pe, port) | 0x00000000UL) |
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#define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL) |
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#define IO7_IO_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFF000000UL) |
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#define IO7_CSR_PHYS(pe, port, off) \ |
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(IO7_HOSE(pe, port) | 0xFF800000UL | (off)) |
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#define IO7_CSRS_PHYS(pe, port) (IO7_CSR_PHYS(pe, port, 0UL)) |
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#define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL)) |
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#define IO7_MEM_KERN(pe, port) (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port))) |
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#define IO7_CONF_KERN(pe, port) (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port))) |
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#define IO7_IO_KERN(pe, port) (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port))) |
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#define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off))) |
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#define IO7_CSRS_KERN(pe, port) (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port))) |
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#define IO7_PORT7_CSRS_KERN(pe) (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe))) |
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#define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7) |
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#define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7) |
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#define IO7_MEM_SPACE (2UL * 1024 * 1024 * 1024) /* 2GB MEM */ |
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#define IO7_IO_SPACE (8UL * 1024 * 1024) /* 8MB I/O */ |
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/* |
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* Offset between ram physical addresses and pci64 DAC addresses |
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*/ |
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#define IO7_DAC_OFFSET (1UL << 49) |
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/* |
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* This is needed to satisify the IO() macro used in initializing the machvec |
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*/ |
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#define MARVEL_IACK_SC \ |
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((unsigned long) \ |
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(&(((io7_ioport_csrs *)IO7_CSRS_KERN(0, 0))->POx_IACK_SPECIAL))) |
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#ifdef __KERNEL__ |
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/* |
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* IO7 structs |
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*/ |
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#define IO7_NUM_PORTS 4 |
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#define IO7_AGP_PORT 3 |
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struct io7_port { |
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struct io7 *io7; |
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struct pci_controller *hose; |
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int enabled; |
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unsigned int port; |
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io7_ioport_csrs *csrs; |
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unsigned long saved_wbase[4]; |
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unsigned long saved_wmask[4]; |
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unsigned long saved_tbase[4]; |
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}; |
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struct io7 { |
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struct io7 *next; |
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unsigned int pe; |
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io7_port7_csrs *csrs; |
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struct io7_port ports[IO7_NUM_PORTS]; |
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raw_spinlock_t irq_lock; |
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}; |
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#ifndef __EXTERN_INLINE |
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# define __EXTERN_INLINE extern inline |
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# define __IO_EXTERN_INLINE |
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#endif |
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/* |
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* I/O functions. All access through linear space. |
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*/ |
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/* |
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* Memory functions. All accesses through linear space. |
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*/ |
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#define vucp volatile unsigned char __force * |
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#define vusp volatile unsigned short __force * |
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extern unsigned int marvel_ioread8(const void __iomem *); |
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extern void marvel_iowrite8(u8 b, void __iomem *); |
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__EXTERN_INLINE unsigned int marvel_ioread16(const void __iomem *addr) |
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{ |
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return __kernel_ldwu(*(vusp)addr); |
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} |
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__EXTERN_INLINE void marvel_iowrite16(u16 b, void __iomem *addr) |
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{ |
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__kernel_stw(b, *(vusp)addr); |
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} |
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extern void __iomem *marvel_ioremap(unsigned long addr, unsigned long size); |
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extern void marvel_iounmap(volatile void __iomem *addr); |
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extern void __iomem *marvel_ioportmap (unsigned long addr); |
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__EXTERN_INLINE int marvel_is_ioaddr(unsigned long addr) |
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{ |
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return (addr >> 40) & 1; |
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} |
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extern int marvel_is_mmio(const volatile void __iomem *); |
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#undef vucp |
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#undef vusp |
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#undef __IO_PREFIX |
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#define __IO_PREFIX marvel |
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#define marvel_trivial_rw_bw 1 |
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#define marvel_trivial_rw_lq 1 |
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#define marvel_trivial_io_bw 0 |
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#define marvel_trivial_io_lq 1 |
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#define marvel_trivial_iounmap 0 |
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#include <asm/io_trivial.h> |
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#ifdef __IO_EXTERN_INLINE |
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# undef __EXTERN_INLINE |
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# undef __IO_EXTERN_INLINE |
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#endif |
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#endif /* __KERNEL__ */ |
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#endif /* __ALPHA_MARVEL__H__ */
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