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233 lines
6.6 KiB
233 lines
6.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ALPHA_IRONGATE__H__ |
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#define __ALPHA_IRONGATE__H__ |
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#include <linux/types.h> |
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#include <asm/compiler.h> |
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/* |
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* IRONGATE is the internal name for the AMD-751 K7 core logic chipset |
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* which provides memory controller and PCI access for NAUTILUS-based |
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* EV6 (21264) systems. |
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* |
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* This file is based on: |
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* |
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* IronGate management library, (c) 1999 Alpha Processor, Inc. |
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* Copyright (C) 1999 Alpha Processor, Inc., |
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* (David Daniel, Stig Telfer, Soohoon Lee) |
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*/ |
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/* |
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* The 21264 supports, and internally recognizes, a 44-bit physical |
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* address space that is divided equally between memory address space |
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* and I/O address space. Memory address space resides in the lower |
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* half of the physical address space (PA[43]=0) and I/O address space |
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* resides in the upper half of the physical address space (PA[43]=1). |
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*/ |
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/* |
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* Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access |
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* through the routines given is 32-bit. |
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* |
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* The first 0x40 bytes are standard as per the PCI spec. |
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*/ |
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typedef volatile __u32 igcsr32; |
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typedef struct { |
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igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */ |
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igcsr32 stat_cmd; /* 0x04 - status, command */ |
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igcsr32 class; /* 0x08 - class code, rev ID */ |
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igcsr32 latency; /* 0x0C - header type, PCI latency */ |
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igcsr32 bar0; /* 0x10 - BAR0 - AGP */ |
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igcsr32 bar1; /* 0x14 - BAR1 - GART */ |
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igcsr32 bar2; /* 0x18 - Power Management reg block */ |
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igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */ |
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igcsr32 capptr; /* 0x34 - Capabilities pointer */ |
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igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */ |
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igcsr32 bacsr10; /* 0x40 - base address chip selects */ |
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igcsr32 bacsr32; /* 0x44 - base address chip selects */ |
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igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects |
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761: ECC, mode/status */ |
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igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */ |
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igcsr32 drammap; /* 0x50 - address mapping control */ |
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igcsr32 dramtm; /* 0x54 - timing, driver strength */ |
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igcsr32 dramms; /* 0x58 - DRAM mode/status */ |
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igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */ |
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igcsr32 biu0; /* 0x60 - bus interface unit */ |
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igcsr32 biusip; /* 0x64 - Serial initialisation pkt */ |
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igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */ |
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igcsr32 mro; /* 0x70 - memory request optimiser */ |
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igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */ |
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igcsr32 whami; /* 0x80 - who am I */ |
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igcsr32 pciarb; /* 0x84 - PCI arbitration control */ |
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igcsr32 pcicfg; /* 0x88 - PCI config status */ |
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igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */ |
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igcsr32 pci_mem; /* 0x9C - PCI top of memory, |
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761 only */ |
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/* AGP (bus 1) control registers */ |
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igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */ |
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igcsr32 agpstat; /* 0xA4 - AGP status register */ |
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igcsr32 agpcmd; /* 0xA8 - AGP control register */ |
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igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */ |
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igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */ |
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} Irongate0; |
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typedef struct { |
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igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */ |
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igcsr32 stat_cmd; /* 0x04 - Status and Command regs */ |
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igcsr32 class; /* 0x08 - subclass, baseclass etc */ |
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igcsr32 htype; /* 0x0C - header type (at 0x0E) */ |
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igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */ |
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igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */ |
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igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */ |
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igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */ |
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igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */ |
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igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */ |
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igcsr32 io_baselim; /* 0x30 - IO base, IO limit */ |
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igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */ |
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igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */ |
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} Irongate1; |
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extern igcsr32 *IronECC; |
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/* |
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* Memory spaces: |
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*/ |
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/* Irongate is consistent with a subset of the Tsunami memory map */ |
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#ifdef USE_48_BIT_KSEG |
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#define IRONGATE_BIAS 0x80000000000UL |
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#else |
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#define IRONGATE_BIAS 0x10000000000UL |
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#endif |
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#define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL) |
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#define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL) |
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#define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL) |
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#define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL) |
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/* |
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* PCI Configuration space accesses are formed like so: |
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* |
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* 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 : |
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* : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 : |
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* ---bus numer--- -device-- -fun- ---register---- |
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*/ |
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#define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \ |
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((dev)<<11) | \ |
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((fun)<<8) | \ |
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(reg) ) |
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#define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0)) |
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#define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0)) |
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/* |
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* Data structure for handling IRONGATE machine checks: |
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* This is the standard OSF logout frame |
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*/ |
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#define SCB_Q_SYSERR 0x620 /* OSF definitions */ |
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#define SCB_Q_PROCERR 0x630 |
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#define SCB_Q_SYSMCHK 0x660 |
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#define SCB_Q_PROCMCHK 0x670 |
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struct el_IRONGATE_sysdata_mcheck { |
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__u32 FrameSize; /* Bytes, including this field */ |
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__u32 FrameFlags; /* <31> = Retry, <30> = Second Error */ |
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__u32 CpuOffset; /* Offset to CPU-specific into */ |
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__u32 SystemOffset; /* Offset to system-specific info */ |
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__u32 MCHK_Code; |
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__u32 MCHK_Frame_Rev; |
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__u64 I_STAT; |
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__u64 DC_STAT; |
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__u64 C_ADDR; |
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__u64 DC1_SYNDROME; |
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__u64 DC0_SYNDROME; |
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__u64 C_STAT; |
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__u64 C_STS; |
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__u64 RESERVED0; |
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__u64 EXC_ADDR; |
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__u64 IER_CM; |
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__u64 ISUM; |
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__u64 MM_STAT; |
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__u64 PAL_BASE; |
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__u64 I_CTL; |
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__u64 PCTX; |
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}; |
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#ifdef __KERNEL__ |
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#ifndef __EXTERN_INLINE |
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#define __EXTERN_INLINE extern inline |
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#define __IO_EXTERN_INLINE |
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#endif |
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/* |
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* I/O functions: |
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* |
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* IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and |
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* K7 can only use linear accesses to get at PCI memory and I/O spaces. |
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*/ |
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/* |
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* Memory functions. All accesses are done through linear space. |
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*/ |
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__EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr) |
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{ |
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return (void __iomem *)(addr + IRONGATE_IO); |
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} |
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extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size); |
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extern void irongate_iounmap(volatile void __iomem *addr); |
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__EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr) |
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{ |
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return addr >= IRONGATE_MEM; |
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} |
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__EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr) |
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{ |
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unsigned long addr = (unsigned long)xaddr; |
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return addr < IRONGATE_IO || addr >= IRONGATE_CONF; |
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} |
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#undef __IO_PREFIX |
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#define __IO_PREFIX irongate |
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#define irongate_trivial_rw_bw 1 |
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#define irongate_trivial_rw_lq 1 |
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#define irongate_trivial_io_bw 1 |
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#define irongate_trivial_io_lq 1 |
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#define irongate_trivial_iounmap 0 |
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#include <asm/io_trivial.h> |
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#ifdef __IO_EXTERN_INLINE |
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#undef __EXTERN_INLINE |
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#undef __IO_EXTERN_INLINE |
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#endif |
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#endif /* __KERNEL__ */ |
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#endif /* __ALPHA_IRONGATE__H__ */
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