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768 lines
18 KiB
768 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Hardware modules present on the DRA7xx chips |
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* |
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
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* |
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* Paul Walmsley |
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* Benoit Cousson |
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* |
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* This file is automatically generated from the OMAP hardware databases. |
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* We respectfully ask that any modifications to this file be coordinated |
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* with the public [email protected] mailing list and the |
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* authors above to ensure that the autogeneration scripts are kept |
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* up-to-date with the file contents. |
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*/ |
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|
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#include <linux/io.h> |
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#include "omap_hwmod.h" |
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#include "omap_hwmod_common_data.h" |
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#include "cm1_7xx.h" |
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#include "cm2_7xx.h" |
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#include "prm7xx.h" |
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#include "soc.h" |
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/* Base offset for all DRA7XX interrupts external to MPUSS */ |
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#define DRA7XX_IRQ_GIC_START 32 |
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/* |
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* IP blocks |
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*/ |
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/* |
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* 'dmm' class |
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* instance(s): dmm |
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*/ |
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static struct omap_hwmod_class dra7xx_dmm_hwmod_class = { |
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.name = "dmm", |
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}; |
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/* dmm */ |
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static struct omap_hwmod dra7xx_dmm_hwmod = { |
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.name = "dmm", |
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.class = &dra7xx_dmm_hwmod_class, |
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.clkdm_name = "emif_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET, |
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}, |
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}, |
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}; |
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/* |
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* 'l3' class |
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* instance(s): l3_instr, l3_main_1, l3_main_2 |
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*/ |
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static struct omap_hwmod_class dra7xx_l3_hwmod_class = { |
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.name = "l3", |
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}; |
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/* l3_instr */ |
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static struct omap_hwmod dra7xx_l3_instr_hwmod = { |
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.name = "l3_instr", |
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.class = &dra7xx_l3_hwmod_class, |
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.clkdm_name = "l3instr_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_HWCTRL, |
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}, |
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}, |
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}; |
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/* l3_main_1 */ |
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static struct omap_hwmod dra7xx_l3_main_1_hwmod = { |
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.name = "l3_main_1", |
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.class = &dra7xx_l3_hwmod_class, |
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.clkdm_name = "l3main1_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, |
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}, |
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}, |
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}; |
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/* l3_main_2 */ |
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static struct omap_hwmod dra7xx_l3_main_2_hwmod = { |
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.name = "l3_main_2", |
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.class = &dra7xx_l3_hwmod_class, |
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.clkdm_name = "l3instr_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_HWCTRL, |
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}, |
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}, |
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}; |
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/* |
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* 'l4' class |
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* instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup |
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*/ |
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static struct omap_hwmod_class dra7xx_l4_hwmod_class = { |
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.name = "l4", |
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}; |
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/* l4_cfg */ |
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static struct omap_hwmod dra7xx_l4_cfg_hwmod = { |
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.name = "l4_cfg", |
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.class = &dra7xx_l4_hwmod_class, |
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.clkdm_name = "l4cfg_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
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}, |
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}, |
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}; |
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/* l4_per1 */ |
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static struct omap_hwmod dra7xx_l4_per1_hwmod = { |
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.name = "l4_per1", |
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.class = &dra7xx_l4_hwmod_class, |
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.clkdm_name = "l4per_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET, |
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
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}, |
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}, |
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}; |
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/* l4_per2 */ |
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static struct omap_hwmod dra7xx_l4_per2_hwmod = { |
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.name = "l4_per2", |
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.class = &dra7xx_l4_hwmod_class, |
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.clkdm_name = "l4per2_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET, |
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
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}, |
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}, |
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}; |
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/* l4_per3 */ |
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static struct omap_hwmod dra7xx_l4_per3_hwmod = { |
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.name = "l4_per3", |
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.class = &dra7xx_l4_hwmod_class, |
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.clkdm_name = "l4per3_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET, |
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
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}, |
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}, |
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}; |
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/* l4_wkup */ |
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static struct omap_hwmod dra7xx_l4_wkup_hwmod = { |
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.name = "l4_wkup", |
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.class = &dra7xx_l4_hwmod_class, |
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.clkdm_name = "wkupaon_clkdm", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, |
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}, |
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}, |
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}; |
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/* |
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* 'atl' class |
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* |
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*/ |
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static struct omap_hwmod_class dra7xx_atl_hwmod_class = { |
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.name = "atl", |
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}; |
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/* atl */ |
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static struct omap_hwmod dra7xx_atl_hwmod = { |
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.name = "atl", |
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.class = &dra7xx_atl_hwmod_class, |
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.clkdm_name = "atl_clkdm", |
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.main_clk = "atl_gfclk_mux", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_SWCTRL, |
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}, |
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}, |
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}; |
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/* |
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* 'bb2d' class |
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* |
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*/ |
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static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = { |
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.name = "bb2d", |
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}; |
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/* bb2d */ |
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static struct omap_hwmod dra7xx_bb2d_hwmod = { |
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.name = "bb2d", |
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.class = &dra7xx_bb2d_hwmod_class, |
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.clkdm_name = "dss_clkdm", |
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.main_clk = "dpll_core_h24x2_ck", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_SWCTRL, |
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}, |
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}, |
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}; |
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/* |
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* 'ctrl_module' class |
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* |
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*/ |
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static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = { |
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.name = "ctrl_module", |
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}; |
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/* ctrl_module_wkup */ |
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static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { |
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.name = "ctrl_module_wkup", |
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.class = &dra7xx_ctrl_module_hwmod_class, |
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.clkdm_name = "wkupaon_clkdm", |
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.prcm = { |
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.omap4 = { |
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, |
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}, |
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}, |
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}; |
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/* |
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* 'gpmc' class |
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* |
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*/ |
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static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = { |
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.rev_offs = 0x0000, |
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.sysc_offs = 0x0010, |
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.syss_offs = 0x0014, |
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = { |
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.name = "gpmc", |
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.sysc = &dra7xx_gpmc_sysc, |
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}; |
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/* gpmc */ |
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static struct omap_hwmod dra7xx_gpmc_hwmod = { |
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.name = "gpmc", |
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.class = &dra7xx_gpmc_hwmod_class, |
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.clkdm_name = "l3main1_clkdm", |
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/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
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.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, |
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.main_clk = "l3_iclk_div", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_HWCTRL, |
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}, |
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}, |
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}; |
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/* |
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* 'mpu' class |
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* |
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*/ |
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static struct omap_hwmod_class dra7xx_mpu_hwmod_class = { |
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.name = "mpu", |
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}; |
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/* mpu */ |
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static struct omap_hwmod dra7xx_mpu_hwmod = { |
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.name = "mpu", |
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.class = &dra7xx_mpu_hwmod_class, |
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.clkdm_name = "mpu_clkdm", |
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.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
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.main_clk = "dpll_mpu_m2_ck", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET, |
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}, |
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}, |
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}; |
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/* |
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* 'PCIE' class |
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* |
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*/ |
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/* |
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* As noted in documentation for _reset() in omap_hwmod.c, the stock reset |
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* functionality of OMAP HWMOD layer does not deassert the hardreset lines |
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* associated with an IP automatically leaving the driver to handle that |
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* by itself. This does not work for PCIeSS which needs the reset lines |
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* deasserted for the driver to start accessing registers. |
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* |
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* We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset |
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* lines after asserting them. |
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*/ |
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int dra7xx_pciess_reset(struct omap_hwmod *oh) |
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{ |
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int i; |
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for (i = 0; i < oh->rst_lines_cnt; i++) { |
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omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name); |
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omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name); |
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} |
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return 0; |
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} |
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static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { |
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.name = "pcie", |
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.reset = dra7xx_pciess_reset, |
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}; |
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/* pcie1 */ |
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static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = { |
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{ .name = "pcie", .rst_shift = 0 }, |
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}; |
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static struct omap_hwmod dra7xx_pciess1_hwmod = { |
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.name = "pcie1", |
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.class = &dra7xx_pciess_hwmod_class, |
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.clkdm_name = "pcie_clkdm", |
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.rst_lines = dra7xx_pciess1_resets, |
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.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets), |
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.main_clk = "l4_root_clk_div", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, |
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.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_SWCTRL, |
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}, |
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}, |
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}; |
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/* pcie2 */ |
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static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = { |
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{ .name = "pcie", .rst_shift = 1 }, |
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}; |
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/* pcie2 */ |
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static struct omap_hwmod dra7xx_pciess2_hwmod = { |
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.name = "pcie2", |
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.class = &dra7xx_pciess_hwmod_class, |
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.clkdm_name = "pcie_clkdm", |
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.rst_lines = dra7xx_pciess2_resets, |
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.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets), |
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.main_clk = "l4_root_clk_div", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, |
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.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_SWCTRL, |
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}, |
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}, |
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}; |
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/* |
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* 'qspi' class |
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* |
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*/ |
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static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = { |
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.rev_offs = 0, |
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.sysc_offs = 0x0010, |
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.sysc_flags = SYSC_HAS_SIDLEMODE, |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
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SIDLE_SMART_WKUP), |
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.sysc_fields = &omap_hwmod_sysc_type2, |
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}; |
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static struct omap_hwmod_class dra7xx_qspi_hwmod_class = { |
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.name = "qspi", |
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.sysc = &dra7xx_qspi_sysc, |
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}; |
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/* qspi */ |
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static struct omap_hwmod dra7xx_qspi_hwmod = { |
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.name = "qspi", |
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.class = &dra7xx_qspi_hwmod_class, |
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.clkdm_name = "l4per2_clkdm", |
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.main_clk = "qspi_gfclk_div", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_SWCTRL, |
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}, |
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}, |
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}; |
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/* |
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* 'sata' class |
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* |
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*/ |
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static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = { |
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.rev_offs = 0x00fc, |
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.sysc_offs = 0x0000, |
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.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
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SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
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MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
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.sysc_fields = &omap_hwmod_sysc_type2, |
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}; |
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static struct omap_hwmod_class dra7xx_sata_hwmod_class = { |
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.name = "sata", |
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.sysc = &dra7xx_sata_sysc, |
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}; |
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/* sata */ |
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static struct omap_hwmod dra7xx_sata_hwmod = { |
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.name = "sata", |
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.class = &dra7xx_sata_hwmod_class, |
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.clkdm_name = "l3init_clkdm", |
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
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.main_clk = "func_48m_fclk", |
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.mpu_rt_idx = 1, |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET, |
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.modulemode = MODULEMODE_SWCTRL, |
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}, |
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}, |
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}; |
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/* |
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* 'vcp' class |
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* |
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*/ |
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static struct omap_hwmod_class dra7xx_vcp_hwmod_class = { |
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.name = "vcp", |
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}; |
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/* vcp1 */ |
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static struct omap_hwmod dra7xx_vcp1_hwmod = { |
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.name = "vcp1", |
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.class = &dra7xx_vcp_hwmod_class, |
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.clkdm_name = "l3main1_clkdm", |
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.main_clk = "l3_iclk_div", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET, |
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}, |
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}, |
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}; |
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/* vcp2 */ |
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static struct omap_hwmod dra7xx_vcp2_hwmod = { |
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.name = "vcp2", |
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.class = &dra7xx_vcp_hwmod_class, |
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.clkdm_name = "l3main1_clkdm", |
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.main_clk = "l3_iclk_div", |
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.prcm = { |
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.omap4 = { |
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET, |
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.context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET, |
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}, |
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}, |
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}; |
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/* |
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* Interfaces |
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*/ |
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/* l3_main_1 -> dmm */ |
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static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = { |
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.master = &dra7xx_l3_main_1_hwmod, |
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.slave = &dra7xx_dmm_hwmod, |
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.clk = "l3_iclk_div", |
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.user = OCP_USER_SDMA, |
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}; |
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|
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/* l3_main_2 -> l3_instr */ |
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static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { |
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.master = &dra7xx_l3_main_2_hwmod, |
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.slave = &dra7xx_l3_instr_hwmod, |
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.clk = "l3_iclk_div", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_cfg -> l3_main_1 */ |
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static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = { |
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.master = &dra7xx_l4_cfg_hwmod, |
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.slave = &dra7xx_l3_main_1_hwmod, |
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.clk = "l3_iclk_div", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* mpu -> l3_main_1 */ |
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static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = { |
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.master = &dra7xx_mpu_hwmod, |
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.slave = &dra7xx_l3_main_1_hwmod, |
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.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU, |
|
}; |
|
|
|
/* l3_main_1 -> l3_main_2 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_l3_main_2_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU, |
|
}; |
|
|
|
/* l4_cfg -> l3_main_2 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = { |
|
.master = &dra7xx_l4_cfg_hwmod, |
|
.slave = &dra7xx_l3_main_2_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> l4_cfg */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_l4_cfg_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> l4_per1 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_l4_per1_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> l4_per2 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_l4_per2_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> l4_per3 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_l4_per3_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> l4_wkup */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_l4_wkup_hwmod, |
|
.clk = "wkupaon_iclk_mux", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_per2 -> atl */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = { |
|
.master = &dra7xx_l4_per2_hwmod, |
|
.slave = &dra7xx_atl_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> bb2d */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_bb2d_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_wkup -> ctrl_module_wkup */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { |
|
.master = &dra7xx_l4_wkup_hwmod, |
|
.slave = &dra7xx_ctrl_module_wkup_hwmod, |
|
.clk = "wkupaon_iclk_mux", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> gpmc */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_gpmc_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_cfg -> mpu */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { |
|
.master = &dra7xx_l4_cfg_hwmod, |
|
.slave = &dra7xx_mpu_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> pciess1 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_pciess1_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_cfg -> pciess1 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = { |
|
.master = &dra7xx_l4_cfg_hwmod, |
|
.slave = &dra7xx_pciess1_hwmod, |
|
.clk = "l4_root_clk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> pciess2 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_pciess2_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_cfg -> pciess2 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = { |
|
.master = &dra7xx_l4_cfg_hwmod, |
|
.slave = &dra7xx_pciess2_hwmod, |
|
.clk = "l4_root_clk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> qspi */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_qspi_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_cfg -> sata */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { |
|
.master = &dra7xx_l4_cfg_hwmod, |
|
.slave = &dra7xx_sata_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> vcp1 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_vcp1_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_per2 -> vcp1 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = { |
|
.master = &dra7xx_l4_per2_hwmod, |
|
.slave = &dra7xx_vcp1_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l3_main_1 -> vcp2 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { |
|
.master = &dra7xx_l3_main_1_hwmod, |
|
.slave = &dra7xx_vcp2_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
/* l4_per2 -> vcp2 */ |
|
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { |
|
.master = &dra7xx_l4_per2_hwmod, |
|
.slave = &dra7xx_vcp2_hwmod, |
|
.clk = "l3_iclk_div", |
|
.user = OCP_USER_MPU | OCP_USER_SDMA, |
|
}; |
|
|
|
static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { |
|
&dra7xx_l3_main_1__dmm, |
|
&dra7xx_l3_main_2__l3_instr, |
|
&dra7xx_l4_cfg__l3_main_1, |
|
&dra7xx_mpu__l3_main_1, |
|
&dra7xx_l3_main_1__l3_main_2, |
|
&dra7xx_l4_cfg__l3_main_2, |
|
&dra7xx_l3_main_1__l4_cfg, |
|
&dra7xx_l3_main_1__l4_per1, |
|
&dra7xx_l3_main_1__l4_per2, |
|
&dra7xx_l3_main_1__l4_per3, |
|
&dra7xx_l3_main_1__l4_wkup, |
|
&dra7xx_l4_per2__atl, |
|
&dra7xx_l3_main_1__bb2d, |
|
&dra7xx_l4_wkup__ctrl_module_wkup, |
|
&dra7xx_l3_main_1__gpmc, |
|
&dra7xx_l4_cfg__mpu, |
|
&dra7xx_l3_main_1__pciess1, |
|
&dra7xx_l4_cfg__pciess1, |
|
&dra7xx_l3_main_1__pciess2, |
|
&dra7xx_l4_cfg__pciess2, |
|
&dra7xx_l3_main_1__qspi, |
|
&dra7xx_l4_cfg__sata, |
|
&dra7xx_l3_main_1__vcp1, |
|
&dra7xx_l4_per2__vcp1, |
|
&dra7xx_l3_main_1__vcp2, |
|
&dra7xx_l4_per2__vcp2, |
|
NULL, |
|
}; |
|
|
|
/* SoC variant specific hwmod links */ |
|
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { |
|
NULL, |
|
}; |
|
|
|
static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = { |
|
NULL, |
|
}; |
|
|
|
int __init dra7xx_hwmod_init(void) |
|
{ |
|
int ret; |
|
|
|
omap_hwmod_init(); |
|
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); |
|
|
|
if (!ret && soc_is_dra74x()) { |
|
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); |
|
} else if (!ret && soc_is_dra72x()) { |
|
ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); |
|
if (!ret && !of_machine_is_compatible("ti,dra718")) |
|
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); |
|
} else if (!ret && soc_is_dra76x()) { |
|
if (!ret && soc_is_dra76x_abz()) |
|
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs); |
|
} |
|
|
|
return ret; |
|
}
|
|
|