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59 lines
2.3 KiB
59 lines
2.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* OMAP54xx CM2 instance offset macros |
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* |
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
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* |
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* Paul Walmsley ([email protected]) |
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* Rajendra Nayak ([email protected]) |
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* Benoit Cousson ([email protected]) |
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* |
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* This file is automatically generated from the OMAP hardware databases. |
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* We respectfully ask that any modifications to this file be coordinated |
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* with the public [email protected] mailing list and the |
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* authors above to ensure that the autogeneration scripts are kept |
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* up-to-date with the file contents. |
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*/ |
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#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H |
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#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H |
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/* CM2 base address */ |
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#define OMAP54XX_CM_CORE_BASE 0x4a008000 |
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#define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ |
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OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) |
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/* CM_CORE instances */ |
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#define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 |
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#define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 |
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#define OMAP54XX_CM_CORE_COREAON_INST 0x0600 |
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#define OMAP54XX_CM_CORE_CORE_INST 0x0700 |
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#define OMAP54XX_CM_CORE_IVA_INST 0x1200 |
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#define OMAP54XX_CM_CORE_CAM_INST 0x1300 |
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#define OMAP54XX_CM_CORE_DSS_INST 0x1400 |
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#define OMAP54XX_CM_CORE_GPU_INST 0x1500 |
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#define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 |
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#define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 |
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/* CM_CORE clockdomain register offsets (from instance start) */ |
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#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 |
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#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 |
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#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 |
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#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 |
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#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 |
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#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 |
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#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 |
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#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 |
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#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 |
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#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 |
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#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 |
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#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 |
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#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 |
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#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 |
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#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 |
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#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 |
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#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 |
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#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 |
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#endif
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