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402 lines
9.9 KiB
402 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Serial Sound Interface (I2S) support for SH7760/SH7780 |
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// |
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// Copyright (c) 2007 Manuel Lauss <[email protected]> |
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// |
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// dont forget to set IPSEL/OMSEL register bits (in your board code) to |
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// enable SSI output pins! |
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/* |
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* LIMITATIONS: |
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* The SSI unit has only one physical data line, so full duplex is |
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* impossible. This can be remedied on the SH7760 by using the |
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* other SSI unit for recording; however the SH7780 has only 1 SSI |
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* unit, and its pins are shared with the AC97 unit, among others. |
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* |
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* FEATURES: |
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* The SSI features "compressed mode": in this mode it continuously |
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* streams PCM data over the I2S lines and uses LRCK as a handshake |
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* signal. Can be used to send compressed data (AC3/DTS) to a DSP. |
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* The number of bits sent over the wire in a frame can be adjusted |
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* and can be independent from the actual sample bit depth. This is |
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* useful to support TDM mode codecs like the AD1939 which have a |
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* fixed TDM slot size, regardless of sample resolution. |
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*/ |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/initval.h> |
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#include <sound/soc.h> |
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#include <asm/io.h> |
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#define SSICR 0x00 |
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#define SSISR 0x04 |
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#define CR_DMAEN (1 << 28) |
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#define CR_CHNL_SHIFT 22 |
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#define CR_CHNL_MASK (3 << CR_CHNL_SHIFT) |
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#define CR_DWL_SHIFT 19 |
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#define CR_DWL_MASK (7 << CR_DWL_SHIFT) |
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#define CR_SWL_SHIFT 16 |
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#define CR_SWL_MASK (7 << CR_SWL_SHIFT) |
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#define CR_SCK_MASTER (1 << 15) /* bitclock master bit */ |
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#define CR_SWS_MASTER (1 << 14) /* wordselect master bit */ |
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#define CR_SCKP (1 << 13) /* I2Sclock polarity */ |
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#define CR_SWSP (1 << 12) /* LRCK polarity */ |
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#define CR_SPDP (1 << 11) |
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#define CR_SDTA (1 << 10) /* i2s alignment (msb/lsb) */ |
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#define CR_PDTA (1 << 9) /* fifo data alignment */ |
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#define CR_DEL (1 << 8) /* delay data by 1 i2sclk */ |
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#define CR_BREN (1 << 7) /* clock gating in burst mode */ |
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#define CR_CKDIV_SHIFT 4 |
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#define CR_CKDIV_MASK (7 << CR_CKDIV_SHIFT) /* bitclock divider */ |
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#define CR_MUTE (1 << 3) /* SSI mute */ |
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#define CR_CPEN (1 << 2) /* compressed mode */ |
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#define CR_TRMD (1 << 1) /* transmit/receive select */ |
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#define CR_EN (1 << 0) /* enable SSI */ |
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#define SSIREG(reg) (*(unsigned long *)(ssi->mmio + (reg))) |
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struct ssi_priv { |
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unsigned long mmio; |
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unsigned long sysclk; |
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int inuse; |
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} ssi_cpu_data[] = { |
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#if defined(CONFIG_CPU_SUBTYPE_SH7760) |
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{ |
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.mmio = 0xFE680000, |
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}, |
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{ |
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.mmio = 0xFE690000, |
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}, |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
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{ |
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.mmio = 0xFFE70000, |
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}, |
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#else |
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#error "Unsupported SuperH SoC" |
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#endif |
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}; |
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/* |
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* track usage of the SSI; it is simplex-only so prevent attempts of |
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* concurrent playback + capture. FIXME: any locking required? |
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*/ |
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static int ssi_startup(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; |
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if (ssi->inuse) { |
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pr_debug("ssi: already in use!\n"); |
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return -EBUSY; |
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} else |
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ssi->inuse = 1; |
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return 0; |
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} |
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static void ssi_shutdown(struct snd_pcm_substream *substream, |
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struct snd_soc_dai *dai) |
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{ |
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struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; |
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ssi->inuse = 0; |
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} |
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static int ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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SSIREG(SSICR) |= CR_DMAEN | CR_EN; |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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SSIREG(SSICR) &= ~(CR_DMAEN | CR_EN); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int ssi_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; |
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unsigned long ssicr = SSIREG(SSICR); |
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unsigned int bits, channels, swl, recv, i; |
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channels = params_channels(params); |
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bits = params->msbits; |
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recv = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 0 : 1; |
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pr_debug("ssi_hw_params() enter\nssicr was %08lx\n", ssicr); |
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pr_debug("bits: %u channels: %u\n", bits, channels); |
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ssicr &= ~(CR_TRMD | CR_CHNL_MASK | CR_DWL_MASK | CR_PDTA | |
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CR_SWL_MASK); |
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/* direction (send/receive) */ |
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if (!recv) |
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ssicr |= CR_TRMD; /* transmit */ |
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/* channels */ |
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if ((channels < 2) || (channels > 8) || (channels & 1)) { |
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pr_debug("ssi: invalid number of channels\n"); |
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return -EINVAL; |
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} |
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ssicr |= ((channels >> 1) - 1) << CR_CHNL_SHIFT; |
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/* DATA WORD LENGTH (DWL): databits in audio sample */ |
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i = 0; |
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switch (bits) { |
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case 32: ++i; |
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case 24: ++i; |
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case 22: ++i; |
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case 20: ++i; |
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case 18: ++i; |
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case 16: ++i; |
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ssicr |= i << CR_DWL_SHIFT; |
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case 8: break; |
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default: |
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pr_debug("ssi: invalid sample width\n"); |
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return -EINVAL; |
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} |
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/* |
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* SYSTEM WORD LENGTH: size in bits of half a frame over the I2S |
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* wires. This is usually bits_per_sample x channels/2; i.e. in |
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* Stereo mode the SWL equals DWL. SWL can be bigger than the |
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* product of (channels_per_slot x samplebits), e.g. for codecs |
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* like the AD1939 which only accept 32bit wide TDM slots. For |
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* "standard" I2S operation we set SWL = chans / 2 * DWL here. |
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* Waiting for ASoC to get TDM support ;-) |
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*/ |
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if ((bits > 16) && (bits <= 24)) { |
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bits = 24; /* these are padded by the SSI */ |
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/*ssicr |= CR_PDTA;*/ /* cpu/data endianness ? */ |
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} |
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i = 0; |
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swl = (bits * channels) / 2; |
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switch (swl) { |
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case 256: ++i; |
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case 128: ++i; |
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case 64: ++i; |
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case 48: ++i; |
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case 32: ++i; |
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case 16: ++i; |
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ssicr |= i << CR_SWL_SHIFT; |
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case 8: break; |
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default: |
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pr_debug("ssi: invalid system word length computed\n"); |
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return -EINVAL; |
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} |
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SSIREG(SSICR) = ssicr; |
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pr_debug("ssi_hw_params() leave\nssicr is now %08lx\n", ssicr); |
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return 0; |
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} |
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static int ssi_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, |
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unsigned int freq, int dir) |
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{ |
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struct ssi_priv *ssi = &ssi_cpu_data[cpu_dai->id]; |
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ssi->sysclk = freq; |
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return 0; |
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} |
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/* |
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* This divider is used to generate the SSI_SCK (I2S bitclock) from the |
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* clock at the HAC_BIT_CLK ("oversampling clock") pin. |
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*/ |
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static int ssi_set_clkdiv(struct snd_soc_dai *dai, int did, int div) |
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{ |
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struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; |
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unsigned long ssicr; |
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int i; |
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i = 0; |
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ssicr = SSIREG(SSICR) & ~CR_CKDIV_MASK; |
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switch (div) { |
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case 16: ++i; |
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case 8: ++i; |
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case 4: ++i; |
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case 2: ++i; |
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SSIREG(SSICR) = ssicr | (i << CR_CKDIV_SHIFT); |
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case 1: break; |
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default: |
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pr_debug("ssi: invalid sck divider %d\n", div); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int ssi_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
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{ |
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struct ssi_priv *ssi = &ssi_cpu_data[dai->id]; |
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unsigned long ssicr = SSIREG(SSICR); |
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pr_debug("ssi_set_fmt()\nssicr was 0x%08lx\n", ssicr); |
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ssicr &= ~(CR_DEL | CR_PDTA | CR_BREN | CR_SWSP | CR_SCKP | |
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CR_SWS_MASTER | CR_SCK_MASTER); |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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break; |
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case SND_SOC_DAIFMT_RIGHT_J: |
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ssicr |= CR_DEL | CR_PDTA; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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ssicr |= CR_DEL; |
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break; |
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default: |
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pr_debug("ssi: unsupported format\n"); |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) { |
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case SND_SOC_DAIFMT_CONT: |
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break; |
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case SND_SOC_DAIFMT_GATED: |
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ssicr |= CR_BREN; |
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break; |
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} |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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ssicr |= CR_SCKP; /* sample data at low clkedge */ |
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break; |
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case SND_SOC_DAIFMT_NB_IF: |
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ssicr |= CR_SCKP | CR_SWSP; |
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break; |
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case SND_SOC_DAIFMT_IB_NF: |
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break; |
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case SND_SOC_DAIFMT_IB_IF: |
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ssicr |= CR_SWSP; /* word select starts low */ |
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break; |
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default: |
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pr_debug("ssi: invalid inversion\n"); |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBM_CFM: |
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break; |
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case SND_SOC_DAIFMT_CBS_CFM: |
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ssicr |= CR_SCK_MASTER; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFS: |
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ssicr |= CR_SWS_MASTER; |
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break; |
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case SND_SOC_DAIFMT_CBS_CFS: |
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ssicr |= CR_SWS_MASTER | CR_SCK_MASTER; |
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break; |
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default: |
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pr_debug("ssi: invalid master/secondary configuration\n"); |
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return -EINVAL; |
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} |
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SSIREG(SSICR) = ssicr; |
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pr_debug("ssi_set_fmt() leave\nssicr is now 0x%08lx\n", ssicr); |
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return 0; |
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} |
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/* the SSI depends on an external clocksource (at HAC_BIT_CLK) even in |
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* Master mode, so really this is board specific; the SSI can do any |
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* rate with the right bitclk and divider settings. |
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*/ |
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#define SSI_RATES \ |
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SNDRV_PCM_RATE_8000_192000 |
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/* the SSI can do 8-32 bit samples, with 8 possible channels */ |
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#define SSI_FMTS \ |
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(SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | \ |
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SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \ |
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SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \ |
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SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_U24_3LE | \ |
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SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE) |
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static const struct snd_soc_dai_ops ssi_dai_ops = { |
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.startup = ssi_startup, |
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.shutdown = ssi_shutdown, |
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.trigger = ssi_trigger, |
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.hw_params = ssi_hw_params, |
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.set_sysclk = ssi_set_sysclk, |
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.set_clkdiv = ssi_set_clkdiv, |
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.set_fmt = ssi_set_fmt, |
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}; |
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static struct snd_soc_dai_driver sh4_ssi_dai[] = { |
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{ |
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.name = "ssi-dai.0", |
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.playback = { |
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.rates = SSI_RATES, |
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.formats = SSI_FMTS, |
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.channels_min = 2, |
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.channels_max = 8, |
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}, |
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.capture = { |
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.rates = SSI_RATES, |
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.formats = SSI_FMTS, |
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.channels_min = 2, |
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.channels_max = 8, |
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}, |
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.ops = &ssi_dai_ops, |
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}, |
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#ifdef CONFIG_CPU_SUBTYPE_SH7760 |
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{ |
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.name = "ssi-dai.1", |
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.playback = { |
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.rates = SSI_RATES, |
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.formats = SSI_FMTS, |
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.channels_min = 2, |
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.channels_max = 8, |
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}, |
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.capture = { |
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.rates = SSI_RATES, |
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.formats = SSI_FMTS, |
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.channels_min = 2, |
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.channels_max = 8, |
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}, |
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.ops = &ssi_dai_ops, |
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}, |
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#endif |
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}; |
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static const struct snd_soc_component_driver sh4_ssi_component = { |
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.name = "sh4-ssi", |
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}; |
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static int sh4_soc_dai_probe(struct platform_device *pdev) |
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{ |
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return devm_snd_soc_register_component(&pdev->dev, &sh4_ssi_component, |
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sh4_ssi_dai, |
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ARRAY_SIZE(sh4_ssi_dai)); |
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} |
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static struct platform_driver sh4_ssi_driver = { |
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.driver = { |
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.name = "sh4-ssi-dai", |
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}, |
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.probe = sh4_soc_dai_probe, |
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}; |
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module_platform_driver(sh4_ssi_driver); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("SuperH onchip SSI (I2S) audio driver"); |
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MODULE_AUTHOR("Manuel Lauss <[email protected]>");
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