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851 lines
20 KiB
851 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for the NVIDIA Tegra pinmux |
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* |
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* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. |
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* |
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* Derived from code: |
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* Copyright (C) 2010 Google, Inc. |
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* Copyright (C) 2010 NVIDIA Corporation |
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* Copyright (C) 2009-2011 ST-Ericsson AB |
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*/ |
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|
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pinctrl/machine.h> |
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#include <linux/pinctrl/pinctrl.h> |
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#include <linux/pinctrl/pinmux.h> |
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#include <linux/pinctrl/pinconf.h> |
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#include <linux/slab.h> |
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#include "../core.h" |
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#include "../pinctrl-utils.h" |
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#include "pinctrl-tegra.h" |
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static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) |
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{ |
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return readl(pmx->regs[bank] + reg); |
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} |
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static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) |
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{ |
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writel_relaxed(val, pmx->regs[bank] + reg); |
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/* make sure pinmux register write completed */ |
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pmx_readl(pmx, bank, reg); |
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} |
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static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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return pmx->soc->ngroups; |
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} |
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static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
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unsigned group) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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return pmx->soc->groups[group].name; |
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} |
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static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, |
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unsigned group, |
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const unsigned **pins, |
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unsigned *num_pins) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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*pins = pmx->soc->groups[group].pins; |
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*num_pins = pmx->soc->groups[group].npins; |
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return 0; |
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} |
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#ifdef CONFIG_DEBUG_FS |
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static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, |
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struct seq_file *s, |
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unsigned offset) |
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{ |
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seq_printf(s, " %s", dev_name(pctldev->dev)); |
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} |
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#endif |
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static const struct cfg_param { |
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const char *property; |
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enum tegra_pinconf_param param; |
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} cfg_params[] = { |
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{"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, |
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{"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, |
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{"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, |
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{"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, |
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{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, |
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{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, |
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{"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, |
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{"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, |
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{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, |
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{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, |
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{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, |
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{"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, |
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{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, |
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{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, |
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{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, |
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{"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE}, |
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}; |
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static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
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struct device_node *np, |
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struct pinctrl_map **map, |
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unsigned *reserved_maps, |
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unsigned *num_maps) |
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{ |
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struct device *dev = pctldev->dev; |
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int ret, i; |
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const char *function; |
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u32 val; |
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unsigned long config; |
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unsigned long *configs = NULL; |
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unsigned num_configs = 0; |
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unsigned reserve; |
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struct property *prop; |
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const char *group; |
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ret = of_property_read_string(np, "nvidia,function", &function); |
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if (ret < 0) { |
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/* EINVAL=missing, which is fine since it's optional */ |
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if (ret != -EINVAL) |
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dev_err(dev, |
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"could not parse property nvidia,function\n"); |
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function = NULL; |
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} |
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for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { |
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ret = of_property_read_u32(np, cfg_params[i].property, &val); |
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if (!ret) { |
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config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); |
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ret = pinctrl_utils_add_config(pctldev, &configs, |
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&num_configs, config); |
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if (ret < 0) |
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goto exit; |
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/* EINVAL=missing, which is fine since it's optional */ |
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} else if (ret != -EINVAL) { |
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dev_err(dev, "could not parse property %s\n", |
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cfg_params[i].property); |
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} |
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} |
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reserve = 0; |
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if (function != NULL) |
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reserve++; |
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if (num_configs) |
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reserve++; |
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ret = of_property_count_strings(np, "nvidia,pins"); |
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if (ret < 0) { |
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dev_err(dev, "could not parse property nvidia,pins\n"); |
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goto exit; |
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} |
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reserve *= ret; |
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ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, |
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num_maps, reserve); |
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if (ret < 0) |
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goto exit; |
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of_property_for_each_string(np, "nvidia,pins", prop, group) { |
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if (function) { |
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ret = pinctrl_utils_add_map_mux(pctldev, map, |
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reserved_maps, num_maps, group, |
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function); |
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if (ret < 0) |
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goto exit; |
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} |
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if (num_configs) { |
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ret = pinctrl_utils_add_map_configs(pctldev, map, |
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reserved_maps, num_maps, group, |
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configs, num_configs, |
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PIN_MAP_TYPE_CONFIGS_GROUP); |
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if (ret < 0) |
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goto exit; |
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} |
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} |
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ret = 0; |
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exit: |
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kfree(configs); |
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return ret; |
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} |
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static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
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struct device_node *np_config, |
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struct pinctrl_map **map, |
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unsigned *num_maps) |
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{ |
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unsigned reserved_maps; |
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struct device_node *np; |
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int ret; |
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reserved_maps = 0; |
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*map = NULL; |
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*num_maps = 0; |
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for_each_child_of_node(np_config, np) { |
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ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map, |
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&reserved_maps, num_maps); |
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if (ret < 0) { |
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pinctrl_utils_free_map(pctldev, *map, |
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*num_maps); |
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of_node_put(np); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static const struct pinctrl_ops tegra_pinctrl_ops = { |
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.get_groups_count = tegra_pinctrl_get_groups_count, |
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.get_group_name = tegra_pinctrl_get_group_name, |
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.get_group_pins = tegra_pinctrl_get_group_pins, |
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#ifdef CONFIG_DEBUG_FS |
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.pin_dbg_show = tegra_pinctrl_pin_dbg_show, |
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#endif |
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.dt_node_to_map = tegra_pinctrl_dt_node_to_map, |
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.dt_free_map = pinctrl_utils_free_map, |
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}; |
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static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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return pmx->soc->nfunctions; |
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} |
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static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, |
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unsigned function) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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return pmx->soc->functions[function].name; |
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} |
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static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, |
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unsigned function, |
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const char * const **groups, |
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unsigned * const num_groups) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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*groups = pmx->soc->functions[function].groups; |
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*num_groups = pmx->soc->functions[function].ngroups; |
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return 0; |
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} |
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static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev, |
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unsigned function, |
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unsigned group) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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const struct tegra_pingroup *g; |
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int i; |
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u32 val; |
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g = &pmx->soc->groups[group]; |
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if (WARN_ON(g->mux_reg < 0)) |
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return -EINVAL; |
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for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { |
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if (g->funcs[i] == function) |
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break; |
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} |
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if (WARN_ON(i == ARRAY_SIZE(g->funcs))) |
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return -EINVAL; |
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val = pmx_readl(pmx, g->mux_bank, g->mux_reg); |
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val &= ~(0x3 << g->mux_bit); |
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val |= i << g->mux_bit; |
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pmx_writel(pmx, val, g->mux_bank, g->mux_reg); |
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return 0; |
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} |
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static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, |
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struct pinctrl_gpio_range *range, |
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unsigned int offset) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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const struct tegra_pingroup *group; |
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u32 value; |
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if (!pmx->soc->sfsel_in_mux) |
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return 0; |
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group = &pmx->soc->groups[offset]; |
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if (group->mux_reg < 0 || group->sfsel_bit < 0) |
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return -EINVAL; |
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value = pmx_readl(pmx, group->mux_bank, group->mux_reg); |
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value &= ~BIT(group->sfsel_bit); |
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pmx_writel(pmx, value, group->mux_bank, group->mux_reg); |
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return 0; |
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} |
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static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, |
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struct pinctrl_gpio_range *range, |
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unsigned int offset) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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const struct tegra_pingroup *group; |
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u32 value; |
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if (!pmx->soc->sfsel_in_mux) |
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return; |
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group = &pmx->soc->groups[offset]; |
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if (group->mux_reg < 0 || group->sfsel_bit < 0) |
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return; |
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value = pmx_readl(pmx, group->mux_bank, group->mux_reg); |
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value |= BIT(group->sfsel_bit); |
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pmx_writel(pmx, value, group->mux_bank, group->mux_reg); |
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} |
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static const struct pinmux_ops tegra_pinmux_ops = { |
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.get_functions_count = tegra_pinctrl_get_funcs_count, |
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.get_function_name = tegra_pinctrl_get_func_name, |
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.get_function_groups = tegra_pinctrl_get_func_groups, |
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.set_mux = tegra_pinctrl_set_mux, |
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.gpio_request_enable = tegra_pinctrl_gpio_request_enable, |
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.gpio_disable_free = tegra_pinctrl_gpio_disable_free, |
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}; |
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static int tegra_pinconf_reg(struct tegra_pmx *pmx, |
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const struct tegra_pingroup *g, |
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enum tegra_pinconf_param param, |
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bool report_err, |
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s8 *bank, s32 *reg, s8 *bit, s8 *width) |
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{ |
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switch (param) { |
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case TEGRA_PINCONF_PARAM_PULL: |
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*bank = g->pupd_bank; |
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*reg = g->pupd_reg; |
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*bit = g->pupd_bit; |
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*width = 2; |
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break; |
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case TEGRA_PINCONF_PARAM_TRISTATE: |
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*bank = g->tri_bank; |
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*reg = g->tri_reg; |
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*bit = g->tri_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_ENABLE_INPUT: |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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*bit = g->einput_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_OPEN_DRAIN: |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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*bit = g->odrain_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_LOCK: |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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*bit = g->lock_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_IORESET: |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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*bit = g->ioreset_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_RCV_SEL: |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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*bit = g->rcv_sel_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: |
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if (pmx->soc->hsm_in_mux) { |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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} else { |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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} |
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*bit = g->hsm_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_SCHMITT: |
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if (pmx->soc->schmitt_in_mux) { |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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} else { |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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} |
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*bit = g->schmitt_bit; |
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*width = 1; |
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break; |
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case TEGRA_PINCONF_PARAM_LOW_POWER_MODE: |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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*bit = g->lpmd_bit; |
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*width = 2; |
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break; |
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case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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*bit = g->drvdn_bit; |
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*width = g->drvdn_width; |
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break; |
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case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH: |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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*bit = g->drvup_bit; |
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*width = g->drvup_width; |
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break; |
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case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING: |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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*bit = g->slwf_bit; |
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*width = g->slwf_width; |
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break; |
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case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING: |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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*bit = g->slwr_bit; |
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*width = g->slwr_width; |
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break; |
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case TEGRA_PINCONF_PARAM_DRIVE_TYPE: |
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if (pmx->soc->drvtype_in_mux) { |
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*bank = g->mux_bank; |
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*reg = g->mux_reg; |
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} else { |
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*bank = g->drv_bank; |
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*reg = g->drv_reg; |
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} |
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*bit = g->drvtype_bit; |
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*width = 2; |
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break; |
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default: |
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dev_err(pmx->dev, "Invalid config param %04x\n", param); |
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return -ENOTSUPP; |
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} |
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if (*reg < 0 || *bit < 0) { |
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if (report_err) { |
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const char *prop = "unknown"; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { |
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if (cfg_params[i].param == param) { |
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prop = cfg_params[i].property; |
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break; |
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} |
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} |
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dev_err(pmx->dev, |
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"Config param %04x (%s) not supported on group %s\n", |
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param, prop, g->name); |
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} |
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return -ENOTSUPP; |
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} |
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return 0; |
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} |
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static int tegra_pinconf_get(struct pinctrl_dev *pctldev, |
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unsigned pin, unsigned long *config) |
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{ |
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dev_err(pctldev->dev, "pin_config_get op not supported\n"); |
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return -ENOTSUPP; |
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} |
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static int tegra_pinconf_set(struct pinctrl_dev *pctldev, |
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unsigned pin, unsigned long *configs, |
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unsigned num_configs) |
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{ |
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dev_err(pctldev->dev, "pin_config_set op not supported\n"); |
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return -ENOTSUPP; |
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} |
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static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, |
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unsigned group, unsigned long *config) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config); |
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u16 arg; |
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const struct tegra_pingroup *g; |
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int ret; |
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s8 bank, bit, width; |
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s32 reg; |
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u32 val, mask; |
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g = &pmx->soc->groups[group]; |
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ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
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&width); |
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if (ret < 0) |
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return ret; |
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val = pmx_readl(pmx, bank, reg); |
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mask = (1 << width) - 1; |
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arg = (val >> bit) & mask; |
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*config = TEGRA_PINCONF_PACK(param, arg); |
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return 0; |
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} |
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static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, |
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unsigned group, unsigned long *configs, |
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unsigned num_configs) |
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{ |
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
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enum tegra_pinconf_param param; |
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u16 arg; |
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const struct tegra_pingroup *g; |
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int ret, i; |
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s8 bank, bit, width; |
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s32 reg; |
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u32 val, mask; |
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g = &pmx->soc->groups[group]; |
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for (i = 0; i < num_configs; i++) { |
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param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]); |
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arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]); |
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ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
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&width); |
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if (ret < 0) |
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return ret; |
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val = pmx_readl(pmx, bank, reg); |
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|
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/* LOCK can't be cleared */ |
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if (param == TEGRA_PINCONF_PARAM_LOCK) { |
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if ((val & BIT(bit)) && !arg) { |
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dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); |
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return -EINVAL; |
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} |
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} |
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|
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/* Special-case Boolean values; allow any non-zero as true */ |
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if (width == 1) |
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arg = !!arg; |
|
|
|
/* Range-check user-supplied value */ |
|
mask = (1 << width) - 1; |
|
if (arg & ~mask) { |
|
dev_err(pctldev->dev, |
|
"config %lx: %x too big for %d bit register\n", |
|
configs[i], arg, width); |
|
return -EINVAL; |
|
} |
|
|
|
/* Update register */ |
|
val &= ~(mask << bit); |
|
val |= arg << bit; |
|
pmx_writel(pmx, val, bank, reg); |
|
} /* for each config */ |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_DEBUG_FS |
|
static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
|
struct seq_file *s, unsigned offset) |
|
{ |
|
} |
|
|
|
static const char *strip_prefix(const char *s) |
|
{ |
|
const char *comma = strchr(s, ','); |
|
if (!comma) |
|
return s; |
|
|
|
return comma + 1; |
|
} |
|
|
|
static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, |
|
struct seq_file *s, unsigned group) |
|
{ |
|
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); |
|
const struct tegra_pingroup *g; |
|
int i, ret; |
|
s8 bank, bit, width; |
|
s32 reg; |
|
u32 val; |
|
|
|
g = &pmx->soc->groups[group]; |
|
|
|
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { |
|
ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, |
|
&bank, ®, &bit, &width); |
|
if (ret < 0) |
|
continue; |
|
|
|
val = pmx_readl(pmx, bank, reg); |
|
val >>= bit; |
|
val &= (1 << width) - 1; |
|
|
|
seq_printf(s, "\n\t%s=%u", |
|
strip_prefix(cfg_params[i].property), val); |
|
} |
|
} |
|
|
|
static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, |
|
struct seq_file *s, |
|
unsigned long config) |
|
{ |
|
enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); |
|
u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); |
|
const char *pname = "unknown"; |
|
int i; |
|
|
|
for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { |
|
if (cfg_params[i].param == param) { |
|
pname = cfg_params[i].property; |
|
break; |
|
} |
|
} |
|
|
|
seq_printf(s, "%s=%d", strip_prefix(pname), arg); |
|
} |
|
#endif |
|
|
|
static const struct pinconf_ops tegra_pinconf_ops = { |
|
.pin_config_get = tegra_pinconf_get, |
|
.pin_config_set = tegra_pinconf_set, |
|
.pin_config_group_get = tegra_pinconf_group_get, |
|
.pin_config_group_set = tegra_pinconf_group_set, |
|
#ifdef CONFIG_DEBUG_FS |
|
.pin_config_dbg_show = tegra_pinconf_dbg_show, |
|
.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, |
|
.pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, |
|
#endif |
|
}; |
|
|
|
static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { |
|
.name = "Tegra GPIOs", |
|
.id = 0, |
|
.base = 0, |
|
}; |
|
|
|
static struct pinctrl_desc tegra_pinctrl_desc = { |
|
.pctlops = &tegra_pinctrl_ops, |
|
.pmxops = &tegra_pinmux_ops, |
|
.confops = &tegra_pinconf_ops, |
|
.owner = THIS_MODULE, |
|
}; |
|
|
|
static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) |
|
{ |
|
int i = 0; |
|
const struct tegra_pingroup *g; |
|
u32 val; |
|
|
|
for (i = 0; i < pmx->soc->ngroups; ++i) { |
|
g = &pmx->soc->groups[i]; |
|
if (g->parked_bitmask > 0) { |
|
unsigned int bank, reg; |
|
|
|
if (g->mux_reg != -1) { |
|
bank = g->mux_bank; |
|
reg = g->mux_reg; |
|
} else { |
|
bank = g->drv_bank; |
|
reg = g->drv_reg; |
|
} |
|
|
|
val = pmx_readl(pmx, bank, reg); |
|
val &= ~g->parked_bitmask; |
|
pmx_writel(pmx, val, bank, reg); |
|
} |
|
} |
|
} |
|
|
|
static size_t tegra_pinctrl_get_bank_size(struct device *dev, |
|
unsigned int bank_id) |
|
{ |
|
struct platform_device *pdev = to_platform_device(dev); |
|
struct resource *res; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); |
|
|
|
return resource_size(res) / 4; |
|
} |
|
|
|
static int tegra_pinctrl_suspend(struct device *dev) |
|
{ |
|
struct tegra_pmx *pmx = dev_get_drvdata(dev); |
|
u32 *backup_regs = pmx->backup_regs; |
|
u32 __iomem *regs; |
|
size_t bank_size; |
|
unsigned int i, k; |
|
|
|
for (i = 0; i < pmx->nbanks; i++) { |
|
bank_size = tegra_pinctrl_get_bank_size(dev, i); |
|
regs = pmx->regs[i]; |
|
for (k = 0; k < bank_size; k++) |
|
*backup_regs++ = readl_relaxed(regs++); |
|
} |
|
|
|
return pinctrl_force_sleep(pmx->pctl); |
|
} |
|
|
|
static int tegra_pinctrl_resume(struct device *dev) |
|
{ |
|
struct tegra_pmx *pmx = dev_get_drvdata(dev); |
|
u32 *backup_regs = pmx->backup_regs; |
|
u32 __iomem *regs; |
|
size_t bank_size; |
|
unsigned int i, k; |
|
|
|
for (i = 0; i < pmx->nbanks; i++) { |
|
bank_size = tegra_pinctrl_get_bank_size(dev, i); |
|
regs = pmx->regs[i]; |
|
for (k = 0; k < bank_size; k++) |
|
writel_relaxed(*backup_regs++, regs++); |
|
} |
|
|
|
/* flush all the prior writes */ |
|
readl_relaxed(pmx->regs[0]); |
|
/* wait for pinctrl register read to complete */ |
|
rmb(); |
|
return 0; |
|
} |
|
|
|
const struct dev_pm_ops tegra_pinctrl_pm = { |
|
.suspend_noirq = &tegra_pinctrl_suspend, |
|
.resume_noirq = &tegra_pinctrl_resume |
|
}; |
|
|
|
static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx) |
|
{ |
|
struct device_node *np; |
|
bool has_prop = false; |
|
|
|
np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible); |
|
if (!np) |
|
return has_prop; |
|
|
|
has_prop = of_find_property(np, "gpio-ranges", NULL); |
|
|
|
of_node_put(np); |
|
|
|
return has_prop; |
|
} |
|
|
|
int tegra_pinctrl_probe(struct platform_device *pdev, |
|
const struct tegra_pinctrl_soc_data *soc_data) |
|
{ |
|
struct tegra_pmx *pmx; |
|
struct resource *res; |
|
int i; |
|
const char **group_pins; |
|
int fn, gn, gfn; |
|
unsigned long backup_regs_size = 0; |
|
|
|
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); |
|
if (!pmx) |
|
return -ENOMEM; |
|
|
|
pmx->dev = &pdev->dev; |
|
pmx->soc = soc_data; |
|
|
|
/* |
|
* Each mux group will appear in 4 functions' list of groups. |
|
* This over-allocates slightly, since not all groups are mux groups. |
|
*/ |
|
pmx->group_pins = devm_kcalloc(&pdev->dev, |
|
soc_data->ngroups * 4, sizeof(*pmx->group_pins), |
|
GFP_KERNEL); |
|
if (!pmx->group_pins) |
|
return -ENOMEM; |
|
|
|
group_pins = pmx->group_pins; |
|
for (fn = 0; fn < soc_data->nfunctions; fn++) { |
|
struct tegra_function *func = &soc_data->functions[fn]; |
|
|
|
func->groups = group_pins; |
|
|
|
for (gn = 0; gn < soc_data->ngroups; gn++) { |
|
const struct tegra_pingroup *g = &soc_data->groups[gn]; |
|
|
|
if (g->mux_reg == -1) |
|
continue; |
|
|
|
for (gfn = 0; gfn < 4; gfn++) |
|
if (g->funcs[gfn] == fn) |
|
break; |
|
if (gfn == 4) |
|
continue; |
|
|
|
BUG_ON(group_pins - pmx->group_pins >= |
|
soc_data->ngroups * 4); |
|
*group_pins++ = g->name; |
|
func->ngroups++; |
|
} |
|
} |
|
|
|
tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; |
|
tegra_pinctrl_desc.name = dev_name(&pdev->dev); |
|
tegra_pinctrl_desc.pins = pmx->soc->pins; |
|
tegra_pinctrl_desc.npins = pmx->soc->npins; |
|
|
|
for (i = 0; ; i++) { |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
|
if (!res) |
|
break; |
|
backup_regs_size += resource_size(res); |
|
} |
|
pmx->nbanks = i; |
|
|
|
pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs), |
|
GFP_KERNEL); |
|
if (!pmx->regs) |
|
return -ENOMEM; |
|
|
|
pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, |
|
GFP_KERNEL); |
|
if (!pmx->backup_regs) |
|
return -ENOMEM; |
|
|
|
for (i = 0; i < pmx->nbanks; i++) { |
|
pmx->regs[i] = devm_platform_ioremap_resource(pdev, i); |
|
if (IS_ERR(pmx->regs[i])) |
|
return PTR_ERR(pmx->regs[i]); |
|
} |
|
|
|
pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx); |
|
if (IS_ERR(pmx->pctl)) { |
|
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
|
return PTR_ERR(pmx->pctl); |
|
} |
|
|
|
tegra_pinctrl_clear_parked_bits(pmx); |
|
|
|
if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) |
|
pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); |
|
|
|
platform_set_drvdata(pdev, pmx); |
|
|
|
dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n"); |
|
|
|
return 0; |
|
}
|
|
|