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985 lines
26 KiB
985 lines
26 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Intel Lynxpoint PCH pinctrl/GPIO driver |
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* |
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* Copyright (c) 2012, 2019, Intel Corporation |
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* Authors: Mathias Nyman <[email protected]> |
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* Andy Shevchenko <[email protected]> |
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*/ |
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|
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#include <linux/acpi.h> |
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#include <linux/bitops.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include <linux/pinctrl/pinctrl.h> |
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#include <linux/pinctrl/pinmux.h> |
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#include <linux/pinctrl/pinconf.h> |
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#include <linux/pinctrl/pinconf-generic.h> |
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#include "pinctrl-intel.h" |
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#define COMMUNITY(p, n) \ |
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{ \ |
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.pin_base = (p), \ |
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.npins = (n), \ |
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} |
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static const struct pinctrl_pin_desc lptlp_pins[] = { |
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PINCTRL_PIN(0, "GP0_UART1_RXD"), |
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PINCTRL_PIN(1, "GP1_UART1_TXD"), |
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PINCTRL_PIN(2, "GP2_UART1_RTSB"), |
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PINCTRL_PIN(3, "GP3_UART1_CTSB"), |
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PINCTRL_PIN(4, "GP4_I2C0_SDA"), |
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PINCTRL_PIN(5, "GP5_I2C0_SCL"), |
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PINCTRL_PIN(6, "GP6_I2C1_SDA"), |
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PINCTRL_PIN(7, "GP7_I2C1_SCL"), |
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PINCTRL_PIN(8, "GP8"), |
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PINCTRL_PIN(9, "GP9"), |
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PINCTRL_PIN(10, "GP10"), |
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PINCTRL_PIN(11, "GP11_SMBALERTB"), |
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PINCTRL_PIN(12, "GP12_LANPHYPC"), |
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PINCTRL_PIN(13, "GP13"), |
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PINCTRL_PIN(14, "GP14"), |
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PINCTRL_PIN(15, "GP15"), |
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PINCTRL_PIN(16, "GP16_MGPIO9"), |
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PINCTRL_PIN(17, "GP17_MGPIO10"), |
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PINCTRL_PIN(18, "GP18_SRC0CLKRQB"), |
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PINCTRL_PIN(19, "GP19_SRC1CLKRQB"), |
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PINCTRL_PIN(20, "GP20_SRC2CLKRQB"), |
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PINCTRL_PIN(21, "GP21_SRC3CLKRQB"), |
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PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"), |
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PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"), |
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PINCTRL_PIN(24, "GP24_MGPIO0"), |
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PINCTRL_PIN(25, "GP25_USBWAKEOUTB"), |
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PINCTRL_PIN(26, "GP26_MGPIO5"), |
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PINCTRL_PIN(27, "GP27_MGPIO6"), |
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PINCTRL_PIN(28, "GP28_MGPIO7"), |
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PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"), |
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PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"), |
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PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"), |
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PINCTRL_PIN(32, "GP32_CLKRUNB"), |
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PINCTRL_PIN(33, "GP33_DEVSLP0"), |
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PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"), |
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PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"), |
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PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"), |
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PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"), |
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PINCTRL_PIN(38, "GP38_DEVSLP1"), |
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PINCTRL_PIN(39, "GP39_DEVSLP2"), |
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PINCTRL_PIN(40, "GP40_OC0B"), |
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PINCTRL_PIN(41, "GP41_OC1B"), |
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PINCTRL_PIN(42, "GP42_OC2B"), |
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PINCTRL_PIN(43, "GP43_OC3B"), |
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PINCTRL_PIN(44, "GP44"), |
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PINCTRL_PIN(45, "GP45_TMS2"), |
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PINCTRL_PIN(46, "GP46_TDO2"), |
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PINCTRL_PIN(47, "GP47"), |
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PINCTRL_PIN(48, "GP48"), |
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PINCTRL_PIN(49, "GP49"), |
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PINCTRL_PIN(50, "GP50"), |
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PINCTRL_PIN(51, "GP51_GSXDOUT"), |
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PINCTRL_PIN(52, "GP52_GSXSLOAD"), |
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PINCTRL_PIN(53, "GP53_GSXDIN"), |
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PINCTRL_PIN(54, "GP54_GSXSRESETB"), |
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PINCTRL_PIN(55, "GP55_GSXCLK"), |
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PINCTRL_PIN(56, "GP56"), |
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PINCTRL_PIN(57, "GP57"), |
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PINCTRL_PIN(58, "GP58"), |
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PINCTRL_PIN(59, "GP59"), |
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PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"), |
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PINCTRL_PIN(61, "GP61_SUS_STATB"), |
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PINCTRL_PIN(62, "GP62_SUSCLK"), |
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PINCTRL_PIN(63, "GP63_SLP_S5B"), |
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PINCTRL_PIN(64, "GP64_SDIO_CLK"), |
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PINCTRL_PIN(65, "GP65_SDIO_CMD"), |
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PINCTRL_PIN(66, "GP66_SDIO_D0"), |
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PINCTRL_PIN(67, "GP67_SDIO_D1"), |
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PINCTRL_PIN(68, "GP68_SDIO_D2"), |
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PINCTRL_PIN(69, "GP69_SDIO_D3"), |
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PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"), |
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PINCTRL_PIN(71, "GP71_MPHYPC"), |
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PINCTRL_PIN(72, "GP72_BATLOWB"), |
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PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"), |
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PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"), |
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PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"), |
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PINCTRL_PIN(76, "GP76_BMBUSYB"), |
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PINCTRL_PIN(77, "GP77_PIRQAB"), |
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PINCTRL_PIN(78, "GP78_PIRQBB"), |
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PINCTRL_PIN(79, "GP79_PIRQCB"), |
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PINCTRL_PIN(80, "GP80_PIRQDB"), |
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PINCTRL_PIN(81, "GP81_SPKR"), |
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PINCTRL_PIN(82, "GP82_RCINB"), |
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PINCTRL_PIN(83, "GP83_GSPI0_CSB"), |
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PINCTRL_PIN(84, "GP84_GSPI0_CLK"), |
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PINCTRL_PIN(85, "GP85_GSPI0_MISO"), |
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PINCTRL_PIN(86, "GP86_GSPI0_MOSI"), |
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PINCTRL_PIN(87, "GP87_GSPI1_CSB"), |
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PINCTRL_PIN(88, "GP88_GSPI1_CLK"), |
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PINCTRL_PIN(89, "GP89_GSPI1_MISO"), |
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PINCTRL_PIN(90, "GP90_GSPI1_MOSI"), |
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PINCTRL_PIN(91, "GP91_UART0_RXD"), |
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PINCTRL_PIN(92, "GP92_UART0_TXD"), |
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PINCTRL_PIN(93, "GP93_UART0_RTSB"), |
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PINCTRL_PIN(94, "GP94_UART0_CTSB"), |
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}; |
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static const struct intel_community lptlp_communities[] = { |
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COMMUNITY(0, 95), |
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}; |
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static const struct intel_pinctrl_soc_data lptlp_soc_data = { |
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.pins = lptlp_pins, |
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.npins = ARRAY_SIZE(lptlp_pins), |
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.communities = lptlp_communities, |
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.ncommunities = ARRAY_SIZE(lptlp_communities), |
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}; |
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/* LynxPoint chipset has support for 95 GPIO pins */ |
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|
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#define LP_NUM_GPIO 95 |
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|
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/* Bitmapped register offsets */ |
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#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ |
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#define LP_IRQ2IOXAPIC 0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */ |
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#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */ |
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#define LP_INT_STAT 0x80 |
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#define LP_INT_ENABLE 0x90 |
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/* Each pin has two 32 bit config registers, starting at 0x100 */ |
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#define LP_CONFIG1 0x100 |
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#define LP_CONFIG2 0x104 |
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|
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/* LP_CONFIG1 reg bits */ |
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#define OUT_LVL_BIT BIT(31) |
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#define IN_LVL_BIT BIT(30) |
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#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */ |
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#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */ |
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#define DIR_BIT BIT(2) /* 0: Output, 1: Input */ |
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#define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */ |
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#define USE_SEL_NATIVE (0 << 0) |
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#define USE_SEL_GPIO (1 << 0) |
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|
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/* LP_CONFIG2 reg bits */ |
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#define GPINDIS_BIT BIT(2) /* disable input sensing */ |
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#define GPIWP_MASK GENMASK(1, 0) /* weak pull options */ |
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#define GPIWP_NONE 0 /* none */ |
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#define GPIWP_DOWN 1 /* weak pull down */ |
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#define GPIWP_UP 2 /* weak pull up */ |
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|
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/* |
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* Lynxpoint gpios are controlled through both bitmapped registers and |
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* per gpio specific registers. The bitmapped registers are in chunks of |
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* 3 x 32bit registers to cover all 95 GPIOs |
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* |
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* per gpio specific registers consist of two 32bit registers per gpio |
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* (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of |
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* 190 config registers. |
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* |
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* A simplified view of the register layout look like this: |
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* |
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* LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers) |
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* LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63 |
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* LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 |
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* ... |
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* LP_INT_ENABLE[31:0] ... |
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* LP_INT_ENABLE[63:32] ... |
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* LP_INT_ENABLE[94:64] ... |
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* LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) |
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* LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 |
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* LP1_CONFIG1 (gpio 1) config1 reg for gpio 1 |
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* LP1_CONFIG2 (gpio 1) config2 reg for gpio 1 |
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* LP2_CONFIG1 (gpio 2) ... |
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* LP2_CONFIG2 (gpio 2) ... |
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* ... |
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* LP94_CONFIG1 (gpio 94) ... |
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* LP94_CONFIG2 (gpio 94) ... |
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* |
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* IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55. |
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*/ |
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static struct intel_community *lp_get_community(struct intel_pinctrl *lg, |
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unsigned int pin) |
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{ |
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struct intel_community *comm; |
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int i; |
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for (i = 0; i < lg->ncommunities; i++) { |
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comm = &lg->communities[i]; |
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if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) |
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return comm; |
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} |
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return NULL; |
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} |
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static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset, |
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int reg) |
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{ |
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struct intel_pinctrl *lg = gpiochip_get_data(chip); |
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struct intel_community *comm; |
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int reg_offset; |
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comm = lp_get_community(lg, offset); |
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if (!comm) |
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return NULL; |
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offset -= comm->pin_base; |
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if (reg == LP_CONFIG1 || reg == LP_CONFIG2) |
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/* per gpio specific config registers */ |
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reg_offset = offset * 8; |
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else |
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/* bitmapped registers */ |
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reg_offset = (offset / 32) * 4; |
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return comm->regs + reg_offset + reg; |
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} |
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static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin) |
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{ |
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void __iomem *acpi_use; |
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acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); |
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if (!acpi_use) |
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return true; |
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return !(ioread32(acpi_use) & BIT(pin % 32)); |
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} |
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static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset) |
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{ |
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void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC); |
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u32 value; |
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value = ioread32(ioxapic_use); |
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if (offset >= 8 && offset <= 10) |
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return !!(value & BIT(offset - 8 + 0)); |
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if (offset >= 13 && offset <= 14) |
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return !!(value & BIT(offset - 13 + 3)); |
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if (offset >= 45 && offset <= 55) |
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return !!(value & BIT(offset - 45 + 5)); |
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return false; |
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} |
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static int lp_get_groups_count(struct pinctrl_dev *pctldev) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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return lg->soc->ngroups; |
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} |
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static const char *lp_get_group_name(struct pinctrl_dev *pctldev, |
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unsigned int selector) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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return lg->soc->groups[selector].name; |
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} |
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static int lp_get_group_pins(struct pinctrl_dev *pctldev, |
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unsigned int selector, |
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const unsigned int **pins, |
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unsigned int *num_pins) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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*pins = lg->soc->groups[selector].pins; |
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*num_pins = lg->soc->groups[selector].npins; |
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return 0; |
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} |
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static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
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unsigned int pin) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); |
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void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); |
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u32 value, mode; |
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value = ioread32(reg); |
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mode = value & USE_SEL_MASK; |
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if (mode == USE_SEL_GPIO) |
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seq_puts(s, "GPIO "); |
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else |
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seq_printf(s, "mode %d ", mode); |
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seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2)); |
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if (lp_gpio_acpi_use(lg, pin)) |
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seq_puts(s, " [ACPI]"); |
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} |
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static const struct pinctrl_ops lptlp_pinctrl_ops = { |
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.get_groups_count = lp_get_groups_count, |
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.get_group_name = lp_get_group_name, |
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.get_group_pins = lp_get_group_pins, |
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.pin_dbg_show = lp_pin_dbg_show, |
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}; |
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static int lp_get_functions_count(struct pinctrl_dev *pctldev) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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return lg->soc->nfunctions; |
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} |
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static const char *lp_get_function_name(struct pinctrl_dev *pctldev, |
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unsigned int selector) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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return lg->soc->functions[selector].name; |
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} |
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static int lp_get_function_groups(struct pinctrl_dev *pctldev, |
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unsigned int selector, |
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const char * const **groups, |
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unsigned int *num_groups) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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*groups = lg->soc->functions[selector].groups; |
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*num_groups = lg->soc->functions[selector].ngroups; |
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return 0; |
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} |
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static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev, |
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unsigned int function, unsigned int group) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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const struct intel_pingroup *grp = &lg->soc->groups[group]; |
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unsigned long flags; |
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int i; |
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raw_spin_lock_irqsave(&lg->lock, flags); |
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/* Now enable the mux setting for each pin in the group */ |
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for (i = 0; i < grp->npins; i++) { |
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void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1); |
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u32 value; |
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value = ioread32(reg); |
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value &= ~USE_SEL_MASK; |
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if (grp->modes) |
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value |= grp->modes[i]; |
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else |
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value |= grp->mode; |
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iowrite32(value, reg); |
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} |
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raw_spin_unlock_irqrestore(&lg->lock, flags); |
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return 0; |
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} |
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static void lp_gpio_enable_input(void __iomem *reg) |
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{ |
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iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg); |
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} |
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static void lp_gpio_disable_input(void __iomem *reg) |
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{ |
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iowrite32(ioread32(reg) | GPINDIS_BIT, reg); |
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} |
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static int lp_gpio_request_enable(struct pinctrl_dev *pctldev, |
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struct pinctrl_gpio_range *range, |
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unsigned int pin) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); |
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void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); |
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unsigned long flags; |
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u32 value; |
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|
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pm_runtime_get(lg->dev); |
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raw_spin_lock_irqsave(&lg->lock, flags); |
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|
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/* |
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* Reconfigure pin to GPIO mode if needed and issue a warning, |
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* since we expect firmware to configure it properly. |
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*/ |
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value = ioread32(reg); |
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if ((value & USE_SEL_MASK) != USE_SEL_GPIO) { |
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iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg); |
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dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); |
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} |
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/* Enable input sensing */ |
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lp_gpio_enable_input(conf2); |
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|
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raw_spin_unlock_irqrestore(&lg->lock, flags); |
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|
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return 0; |
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} |
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static void lp_gpio_disable_free(struct pinctrl_dev *pctldev, |
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struct pinctrl_gpio_range *range, |
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unsigned int pin) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&lg->lock, flags); |
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|
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/* Disable input sensing */ |
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lp_gpio_disable_input(conf2); |
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|
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raw_spin_unlock_irqrestore(&lg->lock, flags); |
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|
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pm_runtime_put(lg->dev); |
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} |
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static int lp_gpio_set_direction(struct pinctrl_dev *pctldev, |
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struct pinctrl_gpio_range *range, |
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unsigned int pin, bool input) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
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void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); |
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unsigned long flags; |
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u32 value; |
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raw_spin_lock_irqsave(&lg->lock, flags); |
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|
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value = ioread32(reg); |
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value &= ~DIR_BIT; |
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if (input) { |
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value |= DIR_BIT; |
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} else { |
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/* |
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* Before making any direction modifications, do a check if GPIO |
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* is set for direct IRQ. On Lynxpoint, setting GPIO to output |
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* does not make sense, so let's at least warn the caller before |
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* they shoot themselves in the foot. |
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*/ |
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WARN(lp_gpio_ioxapic_use(&lg->chip, pin), |
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"Potential Error: Setting GPIO to output with IOxAPIC redirection"); |
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} |
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iowrite32(value, reg); |
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|
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raw_spin_unlock_irqrestore(&lg->lock, flags); |
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|
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return 0; |
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} |
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|
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static const struct pinmux_ops lptlp_pinmux_ops = { |
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.get_functions_count = lp_get_functions_count, |
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.get_function_name = lp_get_function_name, |
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.get_function_groups = lp_get_function_groups, |
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.set_mux = lp_pinmux_set_mux, |
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.gpio_request_enable = lp_gpio_request_enable, |
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.gpio_disable_free = lp_gpio_disable_free, |
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.gpio_set_direction = lp_gpio_set_direction, |
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}; |
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|
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static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, |
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unsigned long *config) |
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{ |
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struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
|
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); |
|
enum pin_config_param param = pinconf_to_config_param(*config); |
|
unsigned long flags; |
|
u32 value, pull; |
|
u16 arg; |
|
|
|
raw_spin_lock_irqsave(&lg->lock, flags); |
|
value = ioread32(conf2); |
|
raw_spin_unlock_irqrestore(&lg->lock, flags); |
|
|
|
pull = value & GPIWP_MASK; |
|
|
|
switch (param) { |
|
case PIN_CONFIG_BIAS_DISABLE: |
|
if (pull != GPIWP_NONE) |
|
return -EINVAL; |
|
arg = 0; |
|
break; |
|
case PIN_CONFIG_BIAS_PULL_DOWN: |
|
if (pull != GPIWP_DOWN) |
|
return -EINVAL; |
|
|
|
arg = 1; |
|
break; |
|
case PIN_CONFIG_BIAS_PULL_UP: |
|
if (pull != GPIWP_UP) |
|
return -EINVAL; |
|
|
|
arg = 1; |
|
break; |
|
default: |
|
return -ENOTSUPP; |
|
} |
|
|
|
*config = pinconf_to_config_packed(param, arg); |
|
|
|
return 0; |
|
} |
|
|
|
static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, |
|
unsigned long *configs, unsigned int num_configs) |
|
{ |
|
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev); |
|
void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); |
|
enum pin_config_param param; |
|
unsigned long flags; |
|
int i, ret = 0; |
|
u32 value; |
|
|
|
raw_spin_lock_irqsave(&lg->lock, flags); |
|
|
|
value = ioread32(conf2); |
|
|
|
for (i = 0; i < num_configs; i++) { |
|
param = pinconf_to_config_param(configs[i]); |
|
|
|
switch (param) { |
|
case PIN_CONFIG_BIAS_DISABLE: |
|
value &= ~GPIWP_MASK; |
|
value |= GPIWP_NONE; |
|
break; |
|
case PIN_CONFIG_BIAS_PULL_DOWN: |
|
value &= ~GPIWP_MASK; |
|
value |= GPIWP_DOWN; |
|
break; |
|
case PIN_CONFIG_BIAS_PULL_UP: |
|
value &= ~GPIWP_MASK; |
|
value |= GPIWP_UP; |
|
break; |
|
default: |
|
ret = -ENOTSUPP; |
|
} |
|
|
|
if (ret) |
|
break; |
|
} |
|
|
|
if (!ret) |
|
iowrite32(value, conf2); |
|
|
|
raw_spin_unlock_irqrestore(&lg->lock, flags); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct pinconf_ops lptlp_pinconf_ops = { |
|
.is_generic = true, |
|
.pin_config_get = lp_pin_config_get, |
|
.pin_config_set = lp_pin_config_set, |
|
}; |
|
|
|
static const struct pinctrl_desc lptlp_pinctrl_desc = { |
|
.pctlops = &lptlp_pinctrl_ops, |
|
.pmxops = &lptlp_pinmux_ops, |
|
.confops = &lptlp_pinconf_ops, |
|
.owner = THIS_MODULE, |
|
}; |
|
|
|
static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset) |
|
{ |
|
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); |
|
return !!(ioread32(reg) & IN_LVL_BIT); |
|
} |
|
|
|
static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) |
|
{ |
|
struct intel_pinctrl *lg = gpiochip_get_data(chip); |
|
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); |
|
unsigned long flags; |
|
|
|
raw_spin_lock_irqsave(&lg->lock, flags); |
|
|
|
if (value) |
|
iowrite32(ioread32(reg) | OUT_LVL_BIT, reg); |
|
else |
|
iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg); |
|
|
|
raw_spin_unlock_irqrestore(&lg->lock, flags); |
|
} |
|
|
|
static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) |
|
{ |
|
return pinctrl_gpio_direction_input(chip->base + offset); |
|
} |
|
|
|
static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, |
|
int value) |
|
{ |
|
lp_gpio_set(chip, offset, value); |
|
|
|
return pinctrl_gpio_direction_output(chip->base + offset); |
|
} |
|
|
|
static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
|
{ |
|
void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1); |
|
|
|
if (ioread32(reg) & DIR_BIT) |
|
return GPIO_LINE_DIRECTION_IN; |
|
|
|
return GPIO_LINE_DIRECTION_OUT; |
|
} |
|
|
|
static void lp_gpio_irq_handler(struct irq_desc *desc) |
|
{ |
|
struct irq_data *data = irq_desc_get_irq_data(desc); |
|
struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
|
struct intel_pinctrl *lg = gpiochip_get_data(gc); |
|
struct irq_chip *chip = irq_data_get_irq_chip(data); |
|
void __iomem *reg, *ena; |
|
unsigned long pending; |
|
u32 base, pin; |
|
|
|
/* check from GPIO controller which pin triggered the interrupt */ |
|
for (base = 0; base < lg->chip.ngpio; base += 32) { |
|
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); |
|
ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); |
|
|
|
/* Only interrupts that are enabled */ |
|
pending = ioread32(reg) & ioread32(ena); |
|
|
|
for_each_set_bit(pin, &pending, 32) { |
|
unsigned int irq; |
|
|
|
irq = irq_find_mapping(lg->chip.irq.domain, base + pin); |
|
generic_handle_irq(irq); |
|
} |
|
} |
|
chip->irq_eoi(data); |
|
} |
|
|
|
static void lp_irq_ack(struct irq_data *d) |
|
{ |
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
|
struct intel_pinctrl *lg = gpiochip_get_data(gc); |
|
u32 hwirq = irqd_to_hwirq(d); |
|
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); |
|
unsigned long flags; |
|
|
|
raw_spin_lock_irqsave(&lg->lock, flags); |
|
iowrite32(BIT(hwirq % 32), reg); |
|
raw_spin_unlock_irqrestore(&lg->lock, flags); |
|
} |
|
|
|
static void lp_irq_unmask(struct irq_data *d) |
|
{ |
|
} |
|
|
|
static void lp_irq_mask(struct irq_data *d) |
|
{ |
|
} |
|
|
|
static void lp_irq_enable(struct irq_data *d) |
|
{ |
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
|
struct intel_pinctrl *lg = gpiochip_get_data(gc); |
|
u32 hwirq = irqd_to_hwirq(d); |
|
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); |
|
unsigned long flags; |
|
|
|
raw_spin_lock_irqsave(&lg->lock, flags); |
|
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg); |
|
raw_spin_unlock_irqrestore(&lg->lock, flags); |
|
} |
|
|
|
static void lp_irq_disable(struct irq_data *d) |
|
{ |
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
|
struct intel_pinctrl *lg = gpiochip_get_data(gc); |
|
u32 hwirq = irqd_to_hwirq(d); |
|
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); |
|
unsigned long flags; |
|
|
|
raw_spin_lock_irqsave(&lg->lock, flags); |
|
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg); |
|
raw_spin_unlock_irqrestore(&lg->lock, flags); |
|
} |
|
|
|
static int lp_irq_set_type(struct irq_data *d, unsigned int type) |
|
{ |
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
|
struct intel_pinctrl *lg = gpiochip_get_data(gc); |
|
u32 hwirq = irqd_to_hwirq(d); |
|
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); |
|
unsigned long flags; |
|
u32 value; |
|
|
|
if (hwirq >= lg->chip.ngpio) |
|
return -EINVAL; |
|
|
|
/* Fail if BIOS reserved pin for ACPI use */ |
|
if (lp_gpio_acpi_use(lg, hwirq)) { |
|
dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); |
|
return -EBUSY; |
|
} |
|
|
|
raw_spin_lock_irqsave(&lg->lock, flags); |
|
value = ioread32(reg); |
|
|
|
/* set both TRIG_SEL and INV bits to 0 for rising edge */ |
|
if (type & IRQ_TYPE_EDGE_RISING) |
|
value &= ~(TRIG_SEL_BIT | INT_INV_BIT); |
|
|
|
/* TRIG_SEL bit 0, INV bit 1 for falling edge */ |
|
if (type & IRQ_TYPE_EDGE_FALLING) |
|
value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT; |
|
|
|
/* TRIG_SEL bit 1, INV bit 0 for level low */ |
|
if (type & IRQ_TYPE_LEVEL_LOW) |
|
value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT; |
|
|
|
/* TRIG_SEL bit 1, INV bit 1 for level high */ |
|
if (type & IRQ_TYPE_LEVEL_HIGH) |
|
value |= TRIG_SEL_BIT | INT_INV_BIT; |
|
|
|
iowrite32(value, reg); |
|
|
|
if (type & IRQ_TYPE_EDGE_BOTH) |
|
irq_set_handler_locked(d, handle_edge_irq); |
|
else if (type & IRQ_TYPE_LEVEL_MASK) |
|
irq_set_handler_locked(d, handle_level_irq); |
|
|
|
raw_spin_unlock_irqrestore(&lg->lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static struct irq_chip lp_irqchip = { |
|
.name = "LP-GPIO", |
|
.irq_ack = lp_irq_ack, |
|
.irq_mask = lp_irq_mask, |
|
.irq_unmask = lp_irq_unmask, |
|
.irq_enable = lp_irq_enable, |
|
.irq_disable = lp_irq_disable, |
|
.irq_set_type = lp_irq_set_type, |
|
.flags = IRQCHIP_SKIP_SET_WAKE, |
|
}; |
|
|
|
static int lp_gpio_irq_init_hw(struct gpio_chip *chip) |
|
{ |
|
struct intel_pinctrl *lg = gpiochip_get_data(chip); |
|
void __iomem *reg; |
|
unsigned int base; |
|
|
|
for (base = 0; base < lg->chip.ngpio; base += 32) { |
|
/* disable gpio pin interrupts */ |
|
reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); |
|
iowrite32(0, reg); |
|
/* Clear interrupt status register */ |
|
reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); |
|
iowrite32(0xffffffff, reg); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int lp_gpio_add_pin_ranges(struct gpio_chip *chip) |
|
{ |
|
struct intel_pinctrl *lg = gpiochip_get_data(chip); |
|
struct device *dev = lg->dev; |
|
int ret; |
|
|
|
ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); |
|
if (ret) |
|
dev_err(dev, "failed to add GPIO pin range\n"); |
|
|
|
return ret; |
|
} |
|
|
|
static int lp_gpio_probe(struct platform_device *pdev) |
|
{ |
|
const struct intel_pinctrl_soc_data *soc; |
|
struct intel_pinctrl *lg; |
|
struct gpio_chip *gc; |
|
struct device *dev = &pdev->dev; |
|
struct resource *io_rc; |
|
void __iomem *regs; |
|
unsigned int i; |
|
int irq, ret; |
|
|
|
soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); |
|
if (!soc) |
|
return -ENODEV; |
|
|
|
lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL); |
|
if (!lg) |
|
return -ENOMEM; |
|
|
|
lg->dev = dev; |
|
lg->soc = soc; |
|
|
|
lg->ncommunities = lg->soc->ncommunities; |
|
lg->communities = devm_kcalloc(dev, lg->ncommunities, |
|
sizeof(*lg->communities), GFP_KERNEL); |
|
if (!lg->communities) |
|
return -ENOMEM; |
|
|
|
lg->pctldesc = lptlp_pinctrl_desc; |
|
lg->pctldesc.name = dev_name(dev); |
|
lg->pctldesc.pins = lg->soc->pins; |
|
lg->pctldesc.npins = lg->soc->npins; |
|
|
|
lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); |
|
if (IS_ERR(lg->pctldev)) { |
|
dev_err(dev, "failed to register pinctrl driver\n"); |
|
return PTR_ERR(lg->pctldev); |
|
} |
|
|
|
platform_set_drvdata(pdev, lg); |
|
|
|
io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0); |
|
if (!io_rc) { |
|
dev_err(dev, "missing IO resources\n"); |
|
return -EINVAL; |
|
} |
|
|
|
regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); |
|
if (!regs) { |
|
dev_err(dev, "failed mapping IO region %pR\n", &io_rc); |
|
return -EBUSY; |
|
} |
|
|
|
for (i = 0; i < lg->soc->ncommunities; i++) { |
|
struct intel_community *comm = &lg->communities[i]; |
|
|
|
*comm = lg->soc->communities[i]; |
|
|
|
comm->regs = regs; |
|
comm->pad_regs = regs + 0x100; |
|
} |
|
|
|
raw_spin_lock_init(&lg->lock); |
|
|
|
gc = &lg->chip; |
|
gc->label = dev_name(dev); |
|
gc->owner = THIS_MODULE; |
|
gc->request = gpiochip_generic_request; |
|
gc->free = gpiochip_generic_free; |
|
gc->direction_input = lp_gpio_direction_input; |
|
gc->direction_output = lp_gpio_direction_output; |
|
gc->get = lp_gpio_get; |
|
gc->set = lp_gpio_set; |
|
gc->set_config = gpiochip_generic_config; |
|
gc->get_direction = lp_gpio_get_direction; |
|
gc->base = -1; |
|
gc->ngpio = LP_NUM_GPIO; |
|
gc->can_sleep = false; |
|
gc->add_pin_ranges = lp_gpio_add_pin_ranges; |
|
gc->parent = dev; |
|
|
|
/* set up interrupts */ |
|
irq = platform_get_irq_optional(pdev, 0); |
|
if (irq > 0) { |
|
struct gpio_irq_chip *girq; |
|
|
|
girq = &gc->irq; |
|
girq->chip = &lp_irqchip; |
|
girq->init_hw = lp_gpio_irq_init_hw; |
|
girq->parent_handler = lp_gpio_irq_handler; |
|
girq->num_parents = 1; |
|
girq->parents = devm_kcalloc(dev, girq->num_parents, |
|
sizeof(*girq->parents), |
|
GFP_KERNEL); |
|
if (!girq->parents) |
|
return -ENOMEM; |
|
girq->parents[0] = irq; |
|
girq->default_type = IRQ_TYPE_NONE; |
|
girq->handler = handle_bad_irq; |
|
} |
|
|
|
ret = devm_gpiochip_add_data(dev, gc, lg); |
|
if (ret) { |
|
dev_err(dev, "failed adding lp-gpio chip\n"); |
|
return ret; |
|
} |
|
|
|
pm_runtime_enable(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int lp_gpio_remove(struct platform_device *pdev) |
|
{ |
|
pm_runtime_disable(&pdev->dev); |
|
return 0; |
|
} |
|
|
|
static int lp_gpio_runtime_suspend(struct device *dev) |
|
{ |
|
return 0; |
|
} |
|
|
|
static int lp_gpio_runtime_resume(struct device *dev) |
|
{ |
|
return 0; |
|
} |
|
|
|
static int lp_gpio_resume(struct device *dev) |
|
{ |
|
struct intel_pinctrl *lg = dev_get_drvdata(dev); |
|
struct gpio_chip *chip = &lg->chip; |
|
const char *dummy; |
|
int i; |
|
|
|
/* on some hardware suspend clears input sensing, re-enable it here */ |
|
for_each_requested_gpio(chip, i, dummy) |
|
lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2)); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops lp_gpio_pm_ops = { |
|
.runtime_suspend = lp_gpio_runtime_suspend, |
|
.runtime_resume = lp_gpio_runtime_resume, |
|
.resume = lp_gpio_resume, |
|
}; |
|
|
|
static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = { |
|
{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data }, |
|
{ "INT3437", (kernel_ulong_t)&lptlp_soc_data }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match); |
|
|
|
static struct platform_driver lp_gpio_driver = { |
|
.probe = lp_gpio_probe, |
|
.remove = lp_gpio_remove, |
|
.driver = { |
|
.name = "lp_gpio", |
|
.pm = &lp_gpio_pm_ops, |
|
.acpi_match_table = lynxpoint_gpio_acpi_match, |
|
}, |
|
}; |
|
|
|
static int __init lp_gpio_init(void) |
|
{ |
|
return platform_driver_register(&lp_gpio_driver); |
|
} |
|
subsys_initcall(lp_gpio_init); |
|
|
|
static void __exit lp_gpio_exit(void) |
|
{ |
|
platform_driver_unregister(&lp_gpio_driver); |
|
} |
|
module_exit(lp_gpio_exit); |
|
|
|
MODULE_AUTHOR("Mathias Nyman (Intel)"); |
|
MODULE_AUTHOR("Andy Shevchenko (Intel)"); |
|
MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:lp_gpio");
|
|
|