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255 lines
6.1 KiB
255 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* PCIe Gen4 host controller driver for NXP Layerscape SoCs |
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* |
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* Copyright 2019-2020 NXP |
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* |
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* Author: Zhiqiang Hou <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/interrupt.h> |
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#include <linux/init.h> |
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#include <linux/of_pci.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/resource.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include "pcie-mobiveil.h" |
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/* LUT and PF control registers */ |
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#define PCIE_LUT_OFF 0x80000 |
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#define PCIE_PF_OFF 0xc0000 |
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#define PCIE_PF_INT_STAT 0x18 |
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#define PF_INT_STAT_PABRST BIT(31) |
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#define PCIE_PF_DBG 0x7fc |
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#define PF_DBG_LTSSM_MASK 0x3f |
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#define PF_DBG_LTSSM_L0 0x2d /* L0 state */ |
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#define PF_DBG_WE BIT(31) |
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#define PF_DBG_PABR BIT(27) |
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#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev) |
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struct ls_pcie_g4 { |
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struct mobiveil_pcie pci; |
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struct delayed_work dwork; |
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int irq; |
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}; |
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static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) |
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{ |
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return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); |
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} |
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static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, |
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u32 off, u32 val) |
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{ |
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iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); |
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} |
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static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) |
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{ |
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struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); |
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u32 state; |
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state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); |
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state = state & PF_DBG_LTSSM_MASK; |
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if (state == PF_DBG_LTSSM_L0) |
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return 1; |
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return 0; |
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} |
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static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie) |
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{ |
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struct mobiveil_pcie *mv_pci = &pcie->pci; |
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mobiveil_csr_writel(mv_pci, 0, PAB_INTP_AMBA_MISC_ENB); |
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} |
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static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4 *pcie) |
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{ |
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struct mobiveil_pcie *mv_pci = &pcie->pci; |
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u32 val; |
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/* Clear the interrupt status */ |
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mobiveil_csr_writel(mv_pci, 0xffffffff, PAB_INTP_AMBA_MISC_STAT); |
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val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET | |
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PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC; |
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mobiveil_csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB); |
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} |
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static int ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) |
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{ |
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struct mobiveil_pcie *mv_pci = &pcie->pci; |
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struct device *dev = &mv_pci->pdev->dev; |
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u32 val, act_stat; |
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int to = 100; |
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/* Poll for pab_csb_reset to set and PAB activity to clear */ |
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do { |
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usleep_range(10, 15); |
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val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT); |
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act_stat = mobiveil_csr_readl(mv_pci, PAB_ACTIVITY_STAT); |
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} while (((val & PF_INT_STAT_PABRST) == 0 || act_stat) && to--); |
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if (to < 0) { |
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dev_err(dev, "Poll PABRST&PABACT timeout\n"); |
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return -EIO; |
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} |
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/* clear PEX_RESET bit in PEX_PF0_DBG register */ |
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val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); |
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val |= PF_DBG_WE; |
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ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); |
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val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); |
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val |= PF_DBG_PABR; |
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ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); |
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val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG); |
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val &= ~PF_DBG_WE; |
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ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val); |
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mobiveil_host_init(mv_pci, true); |
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to = 100; |
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while (!ls_pcie_g4_link_up(mv_pci) && to--) |
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usleep_range(200, 250); |
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if (to < 0) { |
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dev_err(dev, "PCIe link training timeout\n"); |
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return -EIO; |
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} |
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return 0; |
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} |
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static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id) |
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{ |
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struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id; |
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struct mobiveil_pcie *mv_pci = &pcie->pci; |
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u32 val; |
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val = mobiveil_csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT); |
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if (!val) |
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return IRQ_NONE; |
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if (val & PAB_INTP_RESET) { |
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ls_pcie_g4_disable_interrupt(pcie); |
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schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); |
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} |
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mobiveil_csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT); |
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return IRQ_HANDLED; |
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} |
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static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci) |
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{ |
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struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci); |
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struct platform_device *pdev = mv_pci->pdev; |
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struct device *dev = &pdev->dev; |
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int ret; |
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pcie->irq = platform_get_irq_byname(pdev, "intr"); |
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if (pcie->irq < 0) |
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return pcie->irq; |
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ret = devm_request_irq(dev, pcie->irq, ls_pcie_g4_isr, |
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IRQF_SHARED, pdev->name, pcie); |
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if (ret) { |
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dev_err(dev, "Can't register PCIe IRQ, errno = %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static void ls_pcie_g4_reset(struct work_struct *work) |
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{ |
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struct delayed_work *dwork = container_of(work, struct delayed_work, |
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work); |
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struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork); |
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struct mobiveil_pcie *mv_pci = &pcie->pci; |
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u16 ctrl; |
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ctrl = mobiveil_csr_readw(mv_pci, PCI_BRIDGE_CONTROL); |
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ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
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mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL); |
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if (!ls_pcie_g4_reinit_hw(pcie)) |
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return; |
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ls_pcie_g4_enable_interrupt(pcie); |
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} |
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static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = { |
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.interrupt_init = ls_pcie_g4_interrupt_init, |
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}; |
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static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = { |
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.link_up = ls_pcie_g4_link_up, |
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}; |
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static int __init ls_pcie_g4_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct pci_host_bridge *bridge; |
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struct mobiveil_pcie *mv_pci; |
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struct ls_pcie_g4 *pcie; |
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struct device_node *np = dev->of_node; |
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int ret; |
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if (!of_parse_phandle(np, "msi-parent", 0)) { |
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dev_err(dev, "Failed to find msi-parent\n"); |
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return -EINVAL; |
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} |
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); |
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if (!bridge) |
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return -ENOMEM; |
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pcie = pci_host_bridge_priv(bridge); |
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mv_pci = &pcie->pci; |
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mv_pci->pdev = pdev; |
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mv_pci->ops = &ls_pcie_g4_pab_ops; |
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mv_pci->rp.ops = &ls_pcie_g4_rp_ops; |
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mv_pci->rp.bridge = bridge; |
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platform_set_drvdata(pdev, pcie); |
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INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset); |
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ret = mobiveil_pcie_host_probe(mv_pci); |
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if (ret) { |
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dev_err(dev, "Fail to probe\n"); |
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return ret; |
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} |
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ls_pcie_g4_enable_interrupt(pcie); |
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return 0; |
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} |
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static const struct of_device_id ls_pcie_g4_of_match[] = { |
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{ .compatible = "fsl,lx2160a-pcie", }, |
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{ }, |
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}; |
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static struct platform_driver ls_pcie_g4_driver = { |
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.driver = { |
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.name = "layerscape-pcie-gen4", |
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.of_match_table = ls_pcie_g4_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe);
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