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1138 lines
27 KiB
1138 lines
27 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2020 Synopsys, Inc. and/or its affiliates. |
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* Synopsys DesignWare XPCS helpers |
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* |
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* Author: Jose Abreu <[email protected]> |
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*/ |
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|
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#include <linux/delay.h> |
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#include <linux/pcs/pcs-xpcs.h> |
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#include <linux/mdio.h> |
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#include <linux/phylink.h> |
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#include <linux/workqueue.h> |
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#include "pcs-xpcs.h" |
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|
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#define phylink_pcs_to_xpcs(pl_pcs) \ |
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container_of((pl_pcs), struct dw_xpcs, pcs) |
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|
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static const int xpcs_usxgmii_features[] = { |
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ETHTOOL_LINK_MODE_Pause_BIT, |
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ETHTOOL_LINK_MODE_Asym_Pause_BIT, |
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ETHTOOL_LINK_MODE_Autoneg_BIT, |
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ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, |
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ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, |
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ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, |
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ETHTOOL_LINK_MODE_2500baseX_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const int xpcs_10gkr_features[] = { |
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ETHTOOL_LINK_MODE_Pause_BIT, |
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ETHTOOL_LINK_MODE_Asym_Pause_BIT, |
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ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const int xpcs_xlgmii_features[] = { |
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ETHTOOL_LINK_MODE_Pause_BIT, |
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ETHTOOL_LINK_MODE_Asym_Pause_BIT, |
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ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, |
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ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, |
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ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, |
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ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, |
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ETHTOOL_LINK_MODE_50000baseDR_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, |
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ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const int xpcs_sgmii_features[] = { |
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ETHTOOL_LINK_MODE_10baseT_Half_BIT, |
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ETHTOOL_LINK_MODE_10baseT_Full_BIT, |
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ETHTOOL_LINK_MODE_100baseT_Half_BIT, |
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ETHTOOL_LINK_MODE_100baseT_Full_BIT, |
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ETHTOOL_LINK_MODE_1000baseT_Half_BIT, |
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ETHTOOL_LINK_MODE_1000baseT_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const int xpcs_2500basex_features[] = { |
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ETHTOOL_LINK_MODE_Asym_Pause_BIT, |
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ETHTOOL_LINK_MODE_Autoneg_BIT, |
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ETHTOOL_LINK_MODE_2500baseX_Full_BIT, |
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ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
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__ETHTOOL_LINK_MODE_MASK_NBITS, |
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}; |
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static const phy_interface_t xpcs_usxgmii_interfaces[] = { |
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PHY_INTERFACE_MODE_USXGMII, |
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}; |
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static const phy_interface_t xpcs_10gkr_interfaces[] = { |
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PHY_INTERFACE_MODE_10GKR, |
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}; |
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static const phy_interface_t xpcs_xlgmii_interfaces[] = { |
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PHY_INTERFACE_MODE_XLGMII, |
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}; |
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static const phy_interface_t xpcs_sgmii_interfaces[] = { |
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PHY_INTERFACE_MODE_SGMII, |
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}; |
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static const phy_interface_t xpcs_2500basex_interfaces[] = { |
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PHY_INTERFACE_MODE_2500BASEX, |
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PHY_INTERFACE_MODE_MAX, |
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}; |
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enum { |
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DW_XPCS_USXGMII, |
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DW_XPCS_10GKR, |
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DW_XPCS_XLGMII, |
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DW_XPCS_SGMII, |
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DW_XPCS_2500BASEX, |
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DW_XPCS_INTERFACE_MAX, |
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}; |
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struct xpcs_compat { |
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const int *supported; |
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const phy_interface_t *interface; |
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int num_interfaces; |
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int an_mode; |
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int (*pma_config)(struct dw_xpcs *xpcs); |
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}; |
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struct xpcs_id { |
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u32 id; |
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u32 mask; |
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const struct xpcs_compat *compat; |
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}; |
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static const struct xpcs_compat *xpcs_find_compat(const struct xpcs_id *id, |
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phy_interface_t interface) |
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{ |
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int i, j; |
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for (i = 0; i < DW_XPCS_INTERFACE_MAX; i++) { |
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const struct xpcs_compat *compat = &id->compat[i]; |
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for (j = 0; j < compat->num_interfaces; j++) |
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if (compat->interface[j] == interface) |
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return compat; |
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} |
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return NULL; |
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} |
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int xpcs_get_an_mode(struct dw_xpcs *xpcs, phy_interface_t interface) |
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{ |
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const struct xpcs_compat *compat; |
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|
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compat = xpcs_find_compat(xpcs->id, interface); |
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if (!compat) |
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return -ENODEV; |
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|
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return compat->an_mode; |
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} |
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EXPORT_SYMBOL_GPL(xpcs_get_an_mode); |
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static bool __xpcs_linkmode_supported(const struct xpcs_compat *compat, |
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enum ethtool_link_mode_bit_indices linkmode) |
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{ |
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int i; |
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|
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for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) |
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if (compat->supported[i] == linkmode) |
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return true; |
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return false; |
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} |
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#define xpcs_linkmode_supported(compat, mode) \ |
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__xpcs_linkmode_supported(compat, ETHTOOL_LINK_MODE_ ## mode ## _BIT) |
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int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg) |
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{ |
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u32 reg_addr = mdiobus_c45_addr(dev, reg); |
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struct mii_bus *bus = xpcs->mdiodev->bus; |
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int addr = xpcs->mdiodev->addr; |
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return mdiobus_read(bus, addr, reg_addr); |
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} |
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int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val) |
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{ |
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u32 reg_addr = mdiobus_c45_addr(dev, reg); |
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struct mii_bus *bus = xpcs->mdiodev->bus; |
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int addr = xpcs->mdiodev->addr; |
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return mdiobus_write(bus, addr, reg_addr, val); |
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} |
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static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) |
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{ |
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return xpcs_read(xpcs, dev, DW_VENDOR | reg); |
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} |
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static int xpcs_write_vendor(struct dw_xpcs *xpcs, int dev, int reg, |
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u16 val) |
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{ |
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return xpcs_write(xpcs, dev, DW_VENDOR | reg, val); |
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} |
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static int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg) |
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{ |
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return xpcs_read_vendor(xpcs, MDIO_MMD_PCS, reg); |
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} |
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static int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val) |
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{ |
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return xpcs_write_vendor(xpcs, MDIO_MMD_PCS, reg, val); |
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} |
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static int xpcs_poll_reset(struct dw_xpcs *xpcs, int dev) |
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{ |
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/* Poll until the reset bit clears (50ms per retry == 0.6 sec) */ |
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unsigned int retries = 12; |
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int ret; |
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do { |
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msleep(50); |
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ret = xpcs_read(xpcs, dev, MDIO_CTRL1); |
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if (ret < 0) |
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return ret; |
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} while (ret & MDIO_CTRL1_RESET && --retries); |
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return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0; |
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} |
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static int xpcs_soft_reset(struct dw_xpcs *xpcs, |
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const struct xpcs_compat *compat) |
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{ |
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int ret, dev; |
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switch (compat->an_mode) { |
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case DW_AN_C73: |
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dev = MDIO_MMD_PCS; |
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break; |
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case DW_AN_C37_SGMII: |
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case DW_2500BASEX: |
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dev = MDIO_MMD_VEND2; |
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break; |
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default: |
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return -1; |
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} |
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ret = xpcs_write(xpcs, dev, MDIO_CTRL1, MDIO_CTRL1_RESET); |
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if (ret < 0) |
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return ret; |
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return xpcs_poll_reset(xpcs, dev); |
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} |
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#define xpcs_warn(__xpcs, __state, __args...) \ |
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({ \ |
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if ((__state)->link) \ |
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dev_warn(&(__xpcs)->mdiodev->dev, ##__args); \ |
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}) |
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static int xpcs_read_fault_c73(struct dw_xpcs *xpcs, |
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struct phylink_link_state *state) |
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{ |
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int ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (ret & MDIO_STAT1_FAULT) { |
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xpcs_warn(xpcs, state, "Link fault condition detected!\n"); |
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return -EFAULT; |
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} |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT2); |
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if (ret < 0) |
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return ret; |
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if (ret & MDIO_STAT2_RXFAULT) |
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xpcs_warn(xpcs, state, "Receiver fault detected!\n"); |
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if (ret & MDIO_STAT2_TXFAULT) |
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xpcs_warn(xpcs, state, "Transmitter fault detected!\n"); |
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ret = xpcs_read_vendor(xpcs, MDIO_MMD_PCS, DW_VR_XS_PCS_DIG_STS); |
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if (ret < 0) |
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return ret; |
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if (ret & DW_RXFIFO_ERR) { |
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xpcs_warn(xpcs, state, "FIFO fault condition detected!\n"); |
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return -EFAULT; |
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} |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
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if (ret < 0) |
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return ret; |
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if (!(ret & MDIO_PCS_10GBRT_STAT1_BLKLK)) |
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xpcs_warn(xpcs, state, "Link is not locked!\n"); |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT2); |
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if (ret < 0) |
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return ret; |
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if (ret & MDIO_PCS_10GBRT_STAT2_ERR) { |
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xpcs_warn(xpcs, state, "Link has errors!\n"); |
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return -EFAULT; |
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} |
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return 0; |
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} |
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static int xpcs_read_link_c73(struct dw_xpcs *xpcs, bool an) |
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{ |
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bool link = true; |
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int ret; |
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (!(ret & MDIO_STAT1_LSTATUS)) |
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link = false; |
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if (an) { |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
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if (!(ret & MDIO_STAT1_LSTATUS)) |
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link = false; |
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} |
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return link; |
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} |
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static int xpcs_get_max_usxgmii_speed(const unsigned long *supported) |
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{ |
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int max = SPEED_UNKNOWN; |
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if (phylink_test(supported, 1000baseKX_Full)) |
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max = SPEED_1000; |
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if (phylink_test(supported, 2500baseX_Full)) |
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max = SPEED_2500; |
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if (phylink_test(supported, 10000baseKX4_Full)) |
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max = SPEED_10000; |
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if (phylink_test(supported, 10000baseKR_Full)) |
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max = SPEED_10000; |
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return max; |
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} |
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static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed) |
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{ |
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int ret, speed_sel; |
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switch (speed) { |
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case SPEED_10: |
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speed_sel = DW_USXGMII_10; |
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break; |
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case SPEED_100: |
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speed_sel = DW_USXGMII_100; |
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break; |
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case SPEED_1000: |
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speed_sel = DW_USXGMII_1000; |
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break; |
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case SPEED_2500: |
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speed_sel = DW_USXGMII_2500; |
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break; |
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case SPEED_5000: |
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speed_sel = DW_USXGMII_5000; |
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break; |
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case SPEED_10000: |
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speed_sel = DW_USXGMII_10000; |
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break; |
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default: |
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/* Nothing to do here */ |
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return; |
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} |
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ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); |
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if (ret < 0) |
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goto out; |
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ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_EN); |
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if (ret < 0) |
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goto out; |
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ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); |
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if (ret < 0) |
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goto out; |
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ret &= ~DW_USXGMII_SS_MASK; |
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ret |= speed_sel | DW_USXGMII_FULL; |
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ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); |
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if (ret < 0) |
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goto out; |
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ret = xpcs_read_vpcs(xpcs, MDIO_CTRL1); |
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if (ret < 0) |
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goto out; |
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ret = xpcs_write_vpcs(xpcs, MDIO_CTRL1, ret | DW_USXGMII_RST); |
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if (ret < 0) |
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goto out; |
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return; |
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out: |
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pr_err("%s: XPCS access returned %pe\n", __func__, ERR_PTR(ret)); |
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} |
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static int _xpcs_config_aneg_c73(struct dw_xpcs *xpcs, |
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const struct xpcs_compat *compat) |
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{ |
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int ret, adv; |
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|
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/* By default, in USXGMII mode XPCS operates at 10G baud and |
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* replicates data to achieve lower speeds. Hereby, in this |
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* default configuration we need to advertise all supported |
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* modes and not only the ones we want to use. |
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*/ |
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/* SR_AN_ADV3 */ |
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adv = 0; |
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if (xpcs_linkmode_supported(compat, 2500baseX_Full)) |
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adv |= DW_C73_2500KX; |
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|
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/* TODO: 5000baseKR */ |
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ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); |
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if (ret < 0) |
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return ret; |
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|
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/* SR_AN_ADV2 */ |
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adv = 0; |
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if (xpcs_linkmode_supported(compat, 1000baseKX_Full)) |
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adv |= DW_C73_1000KX; |
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if (xpcs_linkmode_supported(compat, 10000baseKX4_Full)) |
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adv |= DW_C73_10000KX4; |
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if (xpcs_linkmode_supported(compat, 10000baseKR_Full)) |
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adv |= DW_C73_10000KR; |
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ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); |
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if (ret < 0) |
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return ret; |
|
|
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/* SR_AN_ADV1 */ |
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adv = DW_C73_AN_ADV_SF; |
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if (xpcs_linkmode_supported(compat, Pause)) |
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adv |= DW_C73_PAUSE; |
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if (xpcs_linkmode_supported(compat, Asym_Pause)) |
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adv |= DW_C73_ASYM_PAUSE; |
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|
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return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); |
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} |
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|
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static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs, |
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const struct xpcs_compat *compat) |
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{ |
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int ret; |
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|
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ret = _xpcs_config_aneg_c73(xpcs, compat); |
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if (ret < 0) |
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return ret; |
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|
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); |
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if (ret < 0) |
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return ret; |
|
|
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ret |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART; |
|
|
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return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); |
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} |
|
|
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static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs, |
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struct phylink_link_state *state, |
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const struct xpcs_compat *compat) |
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{ |
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int ret; |
|
|
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
|
|
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if (ret & MDIO_AN_STAT1_COMPLETE) { |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1); |
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if (ret < 0) |
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return ret; |
|
|
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/* Check if Aneg outcome is valid */ |
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if (!(ret & DW_C73_AN_ADV_SF)) { |
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xpcs_config_aneg_c73(xpcs, compat); |
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return 0; |
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} |
|
|
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return 1; |
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} |
|
|
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return 0; |
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} |
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|
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static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs, |
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struct phylink_link_state *state) |
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{ |
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int ret; |
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|
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ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); |
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if (ret < 0) |
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return ret; |
|
|
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if (!(ret & MDIO_AN_STAT1_LPABLE)) { |
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phylink_clear(state->lp_advertising, Autoneg); |
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return 0; |
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} |
|
|
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phylink_set(state->lp_advertising, Autoneg); |
|
|
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/* Clause 73 outcome */ |
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ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3); |
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if (ret < 0) |
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return ret; |
|
|
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if (ret & DW_C73_2500KX) |
|
phylink_set(state->lp_advertising, 2500baseX_Full); |
|
|
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ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2); |
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if (ret < 0) |
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return ret; |
|
|
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if (ret & DW_C73_1000KX) |
|
phylink_set(state->lp_advertising, 1000baseKX_Full); |
|
if (ret & DW_C73_10000KX4) |
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phylink_set(state->lp_advertising, 10000baseKX4_Full); |
|
if (ret & DW_C73_10000KR) |
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phylink_set(state->lp_advertising, 10000baseKR_Full); |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1); |
|
if (ret < 0) |
|
return ret; |
|
|
|
if (ret & DW_C73_PAUSE) |
|
phylink_set(state->lp_advertising, Pause); |
|
if (ret & DW_C73_ASYM_PAUSE) |
|
phylink_set(state->lp_advertising, Asym_Pause); |
|
|
|
linkmode_and(state->lp_advertising, state->lp_advertising, |
|
state->advertising); |
|
return 0; |
|
} |
|
|
|
static void xpcs_resolve_lpa_c73(struct dw_xpcs *xpcs, |
|
struct phylink_link_state *state) |
|
{ |
|
int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising); |
|
|
|
state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; |
|
state->speed = max_speed; |
|
state->duplex = DUPLEX_FULL; |
|
} |
|
|
|
static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs, |
|
struct phylink_link_state *state) |
|
{ |
|
unsigned long *adv = state->advertising; |
|
int speed = SPEED_UNKNOWN; |
|
int bit; |
|
|
|
for_each_set_bit(bit, adv, __ETHTOOL_LINK_MODE_MASK_NBITS) { |
|
int new_speed = SPEED_UNKNOWN; |
|
|
|
switch (bit) { |
|
case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: |
|
new_speed = SPEED_25000; |
|
break; |
|
case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: |
|
new_speed = SPEED_40000; |
|
break; |
|
case ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: |
|
case ETHTOOL_LINK_MODE_50000baseDR_Full_BIT: |
|
new_speed = SPEED_50000; |
|
break; |
|
case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT: |
|
case ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT: |
|
new_speed = SPEED_100000; |
|
break; |
|
default: |
|
continue; |
|
} |
|
|
|
if (new_speed > speed) |
|
speed = new_speed; |
|
} |
|
|
|
return speed; |
|
} |
|
|
|
static void xpcs_resolve_pma(struct dw_xpcs *xpcs, |
|
struct phylink_link_state *state) |
|
{ |
|
state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX; |
|
state->duplex = DUPLEX_FULL; |
|
|
|
switch (state->interface) { |
|
case PHY_INTERFACE_MODE_10GKR: |
|
state->speed = SPEED_10000; |
|
break; |
|
case PHY_INTERFACE_MODE_XLGMII: |
|
state->speed = xpcs_get_max_xlgmii_speed(xpcs, state); |
|
break; |
|
default: |
|
state->speed = SPEED_UNKNOWN; |
|
break; |
|
} |
|
} |
|
|
|
void xpcs_validate(struct dw_xpcs *xpcs, unsigned long *supported, |
|
struct phylink_link_state *state) |
|
{ |
|
__ETHTOOL_DECLARE_LINK_MODE_MASK(xpcs_supported); |
|
const struct xpcs_compat *compat; |
|
int i; |
|
|
|
/* phylink expects us to report all supported modes with |
|
* PHY_INTERFACE_MODE_NA, just don't limit the supported and |
|
* advertising masks and exit. |
|
*/ |
|
if (state->interface == PHY_INTERFACE_MODE_NA) |
|
return; |
|
|
|
bitmap_zero(xpcs_supported, __ETHTOOL_LINK_MODE_MASK_NBITS); |
|
|
|
compat = xpcs_find_compat(xpcs->id, state->interface); |
|
|
|
/* Populate the supported link modes for this |
|
* PHY interface type |
|
*/ |
|
if (compat) |
|
for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) |
|
set_bit(compat->supported[i], xpcs_supported); |
|
|
|
linkmode_and(supported, supported, xpcs_supported); |
|
linkmode_and(state->advertising, state->advertising, xpcs_supported); |
|
} |
|
EXPORT_SYMBOL_GPL(xpcs_validate); |
|
|
|
int xpcs_config_eee(struct dw_xpcs *xpcs, int mult_fact_100ns, int enable) |
|
{ |
|
int ret; |
|
|
|
if (enable) { |
|
/* Enable EEE */ |
|
ret = DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | |
|
DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | |
|
DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | |
|
mult_fact_100ns << DW_VR_MII_EEE_MULT_FACT_100NS_SHIFT; |
|
} else { |
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0); |
|
if (ret < 0) |
|
return ret; |
|
ret &= ~(DW_VR_MII_EEE_LTX_EN | DW_VR_MII_EEE_LRX_EN | |
|
DW_VR_MII_EEE_TX_QUIET_EN | DW_VR_MII_EEE_RX_QUIET_EN | |
|
DW_VR_MII_EEE_TX_EN_CTRL | DW_VR_MII_EEE_RX_EN_CTRL | |
|
DW_VR_MII_EEE_MULT_FACT_100NS); |
|
} |
|
|
|
ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL0, ret); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret |= DW_VR_MII_EEE_TRN_LPI; |
|
return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_EEE_MCTRL1, ret); |
|
} |
|
EXPORT_SYMBOL_GPL(xpcs_config_eee); |
|
|
|
static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode) |
|
{ |
|
int ret; |
|
|
|
/* For AN for C37 SGMII mode, the settings are :- |
|
* 1) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 10b (SGMII AN) |
|
* 2) VR_MII_AN_CTRL Bit(3) [TX_CONFIG] = 0b (MAC side SGMII) |
|
* DW xPCS used with DW EQoS MAC is always MAC side SGMII. |
|
* 3) VR_MII_DIG_CTRL1 Bit(9) [MAC_AUTO_SW] = 1b (Automatic |
|
* speed/duplex mode change by HW after SGMII AN complete) |
|
* |
|
* Note: Since it is MAC side SGMII, there is no need to set |
|
* SR_MII_AN_ADV. MAC side SGMII receives AN Tx Config from |
|
* PHY about the link state change after C28 AN is completed |
|
* between PHY and Link Partner. There is also no need to |
|
* trigger AN restart for MAC-side SGMII. |
|
*/ |
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret &= ~(DW_VR_MII_PCS_MODE_MASK | DW_VR_MII_TX_CONFIG_MASK); |
|
ret |= (DW_VR_MII_PCS_MODE_C37_SGMII << |
|
DW_VR_MII_AN_CTRL_PCS_MODE_SHIFT & |
|
DW_VR_MII_PCS_MODE_MASK); |
|
ret |= (DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII << |
|
DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT & |
|
DW_VR_MII_TX_CONFIG_MASK); |
|
ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); |
|
if (ret < 0) |
|
return ret; |
|
|
|
if (phylink_autoneg_inband(mode)) |
|
ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; |
|
else |
|
ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; |
|
|
|
return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); |
|
} |
|
|
|
static int xpcs_config_2500basex(struct dw_xpcs *xpcs) |
|
{ |
|
int ret; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); |
|
if (ret < 0) |
|
return ret; |
|
ret |= DW_VR_MII_DIG_CTRL1_2G5_EN; |
|
ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW; |
|
ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); |
|
if (ret < 0) |
|
return ret; |
|
ret &= ~AN_CL37_EN; |
|
ret |= SGMII_SPEED_SS6; |
|
ret &= ~SGMII_SPEED_SS13; |
|
return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret); |
|
} |
|
|
|
int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface, |
|
unsigned int mode) |
|
{ |
|
const struct xpcs_compat *compat; |
|
int ret; |
|
|
|
compat = xpcs_find_compat(xpcs->id, interface); |
|
if (!compat) |
|
return -ENODEV; |
|
|
|
switch (compat->an_mode) { |
|
case DW_AN_C73: |
|
if (phylink_autoneg_inband(mode)) { |
|
ret = xpcs_config_aneg_c73(xpcs, compat); |
|
if (ret) |
|
return ret; |
|
} |
|
break; |
|
case DW_AN_C37_SGMII: |
|
ret = xpcs_config_aneg_c37_sgmii(xpcs, mode); |
|
if (ret) |
|
return ret; |
|
break; |
|
case DW_2500BASEX: |
|
ret = xpcs_config_2500basex(xpcs); |
|
if (ret) |
|
return ret; |
|
break; |
|
default: |
|
return -1; |
|
} |
|
|
|
if (compat->pma_config) { |
|
ret = compat->pma_config(xpcs); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(xpcs_do_config); |
|
|
|
static int xpcs_config(struct phylink_pcs *pcs, unsigned int mode, |
|
phy_interface_t interface, |
|
const unsigned long *advertising, |
|
bool permit_pause_to_mac) |
|
{ |
|
struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); |
|
|
|
return xpcs_do_config(xpcs, interface, mode); |
|
} |
|
|
|
static int xpcs_get_state_c73(struct dw_xpcs *xpcs, |
|
struct phylink_link_state *state, |
|
const struct xpcs_compat *compat) |
|
{ |
|
int ret; |
|
|
|
/* Link needs to be read first ... */ |
|
state->link = xpcs_read_link_c73(xpcs, state->an_enabled) > 0 ? 1 : 0; |
|
|
|
/* ... and then we check the faults. */ |
|
ret = xpcs_read_fault_c73(xpcs, state); |
|
if (ret) { |
|
ret = xpcs_soft_reset(xpcs, compat); |
|
if (ret) |
|
return ret; |
|
|
|
state->link = 0; |
|
|
|
return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND); |
|
} |
|
|
|
if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) { |
|
state->an_complete = true; |
|
xpcs_read_lpa_c73(xpcs, state); |
|
xpcs_resolve_lpa_c73(xpcs, state); |
|
} else if (state->an_enabled) { |
|
state->link = 0; |
|
} else if (state->link) { |
|
xpcs_resolve_pma(xpcs, state); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs, |
|
struct phylink_link_state *state) |
|
{ |
|
int ret; |
|
|
|
/* Reset link_state */ |
|
state->link = false; |
|
state->speed = SPEED_UNKNOWN; |
|
state->duplex = DUPLEX_UNKNOWN; |
|
state->pause = 0; |
|
|
|
/* For C37 SGMII mode, we check DW_VR_MII_AN_INTR_STS for link |
|
* status, speed and duplex. |
|
*/ |
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS); |
|
if (ret < 0) |
|
return false; |
|
|
|
if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) { |
|
int speed_value; |
|
|
|
state->link = true; |
|
|
|
speed_value = (ret & DW_VR_MII_AN_STS_C37_ANSGM_SP) >> |
|
DW_VR_MII_AN_STS_C37_ANSGM_SP_SHIFT; |
|
if (speed_value == DW_VR_MII_C37_ANSGM_SP_1000) |
|
state->speed = SPEED_1000; |
|
else if (speed_value == DW_VR_MII_C37_ANSGM_SP_100) |
|
state->speed = SPEED_100; |
|
else |
|
state->speed = SPEED_10; |
|
|
|
if (ret & DW_VR_MII_AN_STS_C37_ANSGM_FD) |
|
state->duplex = DUPLEX_FULL; |
|
else |
|
state->duplex = DUPLEX_HALF; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void xpcs_get_state(struct phylink_pcs *pcs, |
|
struct phylink_link_state *state) |
|
{ |
|
struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); |
|
const struct xpcs_compat *compat; |
|
int ret; |
|
|
|
compat = xpcs_find_compat(xpcs->id, state->interface); |
|
if (!compat) |
|
return; |
|
|
|
switch (compat->an_mode) { |
|
case DW_AN_C73: |
|
ret = xpcs_get_state_c73(xpcs, state, compat); |
|
if (ret) { |
|
pr_err("xpcs_get_state_c73 returned %pe\n", |
|
ERR_PTR(ret)); |
|
return; |
|
} |
|
break; |
|
case DW_AN_C37_SGMII: |
|
ret = xpcs_get_state_c37_sgmii(xpcs, state); |
|
if (ret) { |
|
pr_err("xpcs_get_state_c37_sgmii returned %pe\n", |
|
ERR_PTR(ret)); |
|
} |
|
break; |
|
default: |
|
return; |
|
} |
|
} |
|
|
|
static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode, |
|
int speed, int duplex) |
|
{ |
|
int val, ret; |
|
|
|
if (phylink_autoneg_inband(mode)) |
|
return; |
|
|
|
switch (speed) { |
|
case SPEED_1000: |
|
val = BMCR_SPEED1000; |
|
break; |
|
case SPEED_100: |
|
val = BMCR_SPEED100; |
|
break; |
|
case SPEED_10: |
|
val = BMCR_SPEED10; |
|
break; |
|
default: |
|
return; |
|
} |
|
|
|
if (duplex == DUPLEX_FULL) |
|
val |= BMCR_FULLDPLX; |
|
|
|
ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); |
|
if (ret) |
|
pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret)); |
|
} |
|
|
|
void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode, |
|
phy_interface_t interface, int speed, int duplex) |
|
{ |
|
struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs); |
|
|
|
if (interface == PHY_INTERFACE_MODE_USXGMII) |
|
return xpcs_config_usxgmii(xpcs, speed); |
|
if (interface == PHY_INTERFACE_MODE_SGMII) |
|
return xpcs_link_up_sgmii(xpcs, mode, speed, duplex); |
|
} |
|
EXPORT_SYMBOL_GPL(xpcs_link_up); |
|
|
|
static u32 xpcs_get_id(struct dw_xpcs *xpcs) |
|
{ |
|
int ret; |
|
u32 id; |
|
|
|
/* First, search C73 PCS using PCS MMD */ |
|
ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID1); |
|
if (ret < 0) |
|
return 0xffffffff; |
|
|
|
id = ret << 16; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_PCS, MII_PHYSID2); |
|
if (ret < 0) |
|
return 0xffffffff; |
|
|
|
/* If Device IDs are not all zeros or all ones, |
|
* we found C73 AN-type device |
|
*/ |
|
if ((id | ret) && (id | ret) != 0xffffffff) |
|
return id | ret; |
|
|
|
/* Next, search C37 PCS using Vendor-Specific MII MMD */ |
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); |
|
if (ret < 0) |
|
return 0xffffffff; |
|
|
|
id = ret << 16; |
|
|
|
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID2); |
|
if (ret < 0) |
|
return 0xffffffff; |
|
|
|
/* If Device IDs are not all zeros, we found C37 AN-type device */ |
|
if (id | ret) |
|
return id | ret; |
|
|
|
return 0xffffffff; |
|
} |
|
|
|
static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { |
|
[DW_XPCS_USXGMII] = { |
|
.supported = xpcs_usxgmii_features, |
|
.interface = xpcs_usxgmii_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_usxgmii_interfaces), |
|
.an_mode = DW_AN_C73, |
|
}, |
|
[DW_XPCS_10GKR] = { |
|
.supported = xpcs_10gkr_features, |
|
.interface = xpcs_10gkr_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_10gkr_interfaces), |
|
.an_mode = DW_AN_C73, |
|
}, |
|
[DW_XPCS_XLGMII] = { |
|
.supported = xpcs_xlgmii_features, |
|
.interface = xpcs_xlgmii_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces), |
|
.an_mode = DW_AN_C73, |
|
}, |
|
[DW_XPCS_SGMII] = { |
|
.supported = xpcs_sgmii_features, |
|
.interface = xpcs_sgmii_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), |
|
.an_mode = DW_AN_C37_SGMII, |
|
}, |
|
[DW_XPCS_2500BASEX] = { |
|
.supported = xpcs_2500basex_features, |
|
.interface = xpcs_2500basex_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_2500basex_features), |
|
.an_mode = DW_2500BASEX, |
|
}, |
|
}; |
|
|
|
static const struct xpcs_compat nxp_sja1105_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { |
|
[DW_XPCS_SGMII] = { |
|
.supported = xpcs_sgmii_features, |
|
.interface = xpcs_sgmii_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), |
|
.an_mode = DW_AN_C37_SGMII, |
|
.pma_config = nxp_sja1105_sgmii_pma_config, |
|
}, |
|
}; |
|
|
|
static const struct xpcs_compat nxp_sja1110_xpcs_compat[DW_XPCS_INTERFACE_MAX] = { |
|
[DW_XPCS_SGMII] = { |
|
.supported = xpcs_sgmii_features, |
|
.interface = xpcs_sgmii_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces), |
|
.an_mode = DW_AN_C37_SGMII, |
|
.pma_config = nxp_sja1110_sgmii_pma_config, |
|
}, |
|
[DW_XPCS_2500BASEX] = { |
|
.supported = xpcs_2500basex_features, |
|
.interface = xpcs_2500basex_interfaces, |
|
.num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces), |
|
.an_mode = DW_2500BASEX, |
|
.pma_config = nxp_sja1110_2500basex_pma_config, |
|
}, |
|
}; |
|
|
|
static const struct xpcs_id xpcs_id_list[] = { |
|
{ |
|
.id = SYNOPSYS_XPCS_ID, |
|
.mask = SYNOPSYS_XPCS_MASK, |
|
.compat = synopsys_xpcs_compat, |
|
}, { |
|
.id = NXP_SJA1105_XPCS_ID, |
|
.mask = SYNOPSYS_XPCS_MASK, |
|
.compat = nxp_sja1105_xpcs_compat, |
|
}, { |
|
.id = NXP_SJA1110_XPCS_ID, |
|
.mask = SYNOPSYS_XPCS_MASK, |
|
.compat = nxp_sja1110_xpcs_compat, |
|
}, |
|
}; |
|
|
|
static const struct phylink_pcs_ops xpcs_phylink_ops = { |
|
.pcs_config = xpcs_config, |
|
.pcs_get_state = xpcs_get_state, |
|
.pcs_link_up = xpcs_link_up, |
|
}; |
|
|
|
struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev, |
|
phy_interface_t interface) |
|
{ |
|
struct dw_xpcs *xpcs; |
|
u32 xpcs_id; |
|
int i, ret; |
|
|
|
xpcs = kzalloc(sizeof(*xpcs), GFP_KERNEL); |
|
if (!xpcs) |
|
return NULL; |
|
|
|
xpcs->mdiodev = mdiodev; |
|
|
|
xpcs_id = xpcs_get_id(xpcs); |
|
|
|
for (i = 0; i < ARRAY_SIZE(xpcs_id_list); i++) { |
|
const struct xpcs_id *entry = &xpcs_id_list[i]; |
|
const struct xpcs_compat *compat; |
|
|
|
if ((xpcs_id & entry->mask) != entry->id) |
|
continue; |
|
|
|
xpcs->id = entry; |
|
|
|
compat = xpcs_find_compat(entry, interface); |
|
if (!compat) { |
|
ret = -ENODEV; |
|
goto out; |
|
} |
|
|
|
xpcs->pcs.ops = &xpcs_phylink_ops; |
|
xpcs->pcs.poll = true; |
|
|
|
ret = xpcs_soft_reset(xpcs, compat); |
|
if (ret) |
|
goto out; |
|
|
|
return xpcs; |
|
} |
|
|
|
ret = -ENODEV; |
|
|
|
out: |
|
kfree(xpcs); |
|
|
|
return ERR_PTR(ret); |
|
} |
|
EXPORT_SYMBOL_GPL(xpcs_create); |
|
|
|
void xpcs_destroy(struct dw_xpcs *xpcs) |
|
{ |
|
kfree(xpcs); |
|
} |
|
EXPORT_SYMBOL_GPL(xpcs_destroy); |
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|