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231 lines
5.4 KiB
231 lines
5.4 KiB
/* |
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* MTD map driver for flash on the DC21285 (the StrongARM-110 companion chip) |
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* |
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* (C) 2000 Nicolas Pitre <[email protected]> |
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* |
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* This code is GPL |
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*/ |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/delay.h> |
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#include <linux/slab.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/map.h> |
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#include <linux/mtd/partitions.h> |
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#include <asm/io.h> |
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#include <asm/hardware/dec21285.h> |
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#include <asm/mach-types.h> |
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static struct mtd_info *dc21285_mtd; |
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#ifdef CONFIG_ARCH_NETWINDER |
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/* |
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* This is really ugly, but it seams to be the only |
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* realiable way to do it, as the cpld state machine |
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* is unpredictible. So we have a 25us penalty per |
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* write access. |
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*/ |
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static void nw_en_write(void) |
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{ |
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unsigned long flags; |
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/* |
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* we want to write a bit pattern XXX1 to Xilinx to enable |
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* the write gate, which will be open for about the next 2ms. |
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*/ |
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raw_spin_lock_irqsave(&nw_gpio_lock, flags); |
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nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE); |
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raw_spin_unlock_irqrestore(&nw_gpio_lock, flags); |
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/* |
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* let the ISA bus to catch on... |
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*/ |
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udelay(25); |
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} |
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#else |
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#define nw_en_write() do { } while (0) |
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#endif |
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static map_word dc21285_read8(struct map_info *map, unsigned long ofs) |
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{ |
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map_word val; |
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val.x[0] = *(uint8_t*)(map->virt + ofs); |
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return val; |
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} |
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static map_word dc21285_read16(struct map_info *map, unsigned long ofs) |
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{ |
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map_word val; |
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val.x[0] = *(uint16_t*)(map->virt + ofs); |
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return val; |
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} |
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static map_word dc21285_read32(struct map_info *map, unsigned long ofs) |
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{ |
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map_word val; |
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val.x[0] = *(uint32_t*)(map->virt + ofs); |
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return val; |
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} |
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static void dc21285_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
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{ |
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memcpy(to, (void*)(map->virt + from), len); |
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} |
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static void dc21285_write8(struct map_info *map, const map_word d, unsigned long adr) |
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{ |
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if (machine_is_netwinder()) |
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nw_en_write(); |
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*CSR_ROMWRITEREG = adr & 3; |
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adr &= ~3; |
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*(uint8_t*)(map->virt + adr) = d.x[0]; |
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} |
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static void dc21285_write16(struct map_info *map, const map_word d, unsigned long adr) |
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{ |
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if (machine_is_netwinder()) |
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nw_en_write(); |
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*CSR_ROMWRITEREG = adr & 3; |
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adr &= ~3; |
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*(uint16_t*)(map->virt + adr) = d.x[0]; |
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} |
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static void dc21285_write32(struct map_info *map, const map_word d, unsigned long adr) |
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{ |
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if (machine_is_netwinder()) |
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nw_en_write(); |
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*(uint32_t*)(map->virt + adr) = d.x[0]; |
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} |
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static void dc21285_copy_to_32(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
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{ |
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while (len > 0) { |
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map_word d; |
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d.x[0] = *((uint32_t*)from); |
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dc21285_write32(map, d, to); |
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from += 4; |
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to += 4; |
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len -= 4; |
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} |
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} |
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static void dc21285_copy_to_16(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
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{ |
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while (len > 0) { |
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map_word d; |
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d.x[0] = *((uint16_t*)from); |
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dc21285_write16(map, d, to); |
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from += 2; |
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to += 2; |
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len -= 2; |
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} |
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} |
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static void dc21285_copy_to_8(struct map_info *map, unsigned long to, const void *from, ssize_t len) |
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{ |
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map_word d; |
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d.x[0] = *((uint8_t*)from); |
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dc21285_write8(map, d, to); |
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from++; |
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to++; |
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len--; |
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} |
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static struct map_info dc21285_map = { |
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.name = "DC21285 flash", |
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.phys = NO_XIP, |
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.size = 16*1024*1024, |
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.copy_from = dc21285_copy_from, |
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}; |
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/* Partition stuff */ |
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static const char * const probes[] = { "RedBoot", "cmdlinepart", NULL }; |
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static int __init init_dc21285(void) |
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{ |
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/* Determine bankwidth */ |
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switch (*CSR_SA110_CNTL & (3<<14)) { |
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case SA110_CNTL_ROMWIDTH_8: |
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dc21285_map.bankwidth = 1; |
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dc21285_map.read = dc21285_read8; |
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dc21285_map.write = dc21285_write8; |
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dc21285_map.copy_to = dc21285_copy_to_8; |
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break; |
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case SA110_CNTL_ROMWIDTH_16: |
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dc21285_map.bankwidth = 2; |
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dc21285_map.read = dc21285_read16; |
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dc21285_map.write = dc21285_write16; |
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dc21285_map.copy_to = dc21285_copy_to_16; |
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break; |
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case SA110_CNTL_ROMWIDTH_32: |
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dc21285_map.bankwidth = 4; |
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dc21285_map.read = dc21285_read32; |
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dc21285_map.write = dc21285_write32; |
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dc21285_map.copy_to = dc21285_copy_to_32; |
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break; |
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default: |
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printk (KERN_ERR "DC21285 flash: undefined bankwidth\n"); |
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return -ENXIO; |
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} |
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printk (KERN_NOTICE "DC21285 flash support (%d-bit bankwidth)\n", |
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dc21285_map.bankwidth*8); |
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/* Let's map the flash area */ |
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dc21285_map.virt = ioremap(DC21285_FLASH, 16*1024*1024); |
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if (!dc21285_map.virt) { |
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printk("Failed to ioremap\n"); |
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return -EIO; |
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} |
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if (machine_is_ebsa285()) { |
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dc21285_mtd = do_map_probe("cfi_probe", &dc21285_map); |
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} else { |
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dc21285_mtd = do_map_probe("jedec_probe", &dc21285_map); |
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} |
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if (!dc21285_mtd) { |
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iounmap(dc21285_map.virt); |
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return -ENXIO; |
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} |
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dc21285_mtd->owner = THIS_MODULE; |
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mtd_device_parse_register(dc21285_mtd, probes, NULL, NULL, 0); |
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if(machine_is_ebsa285()) { |
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/* |
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* Flash timing is determined with bits 19-16 of the |
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* CSR_SA110_CNTL. The value is the number of wait cycles, or |
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* 0 for 16 cycles (the default). Cycles are 20 ns. |
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* Here we use 7 for 140 ns flash chips. |
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*/ |
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/* access time */ |
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*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x000f0000) | (7 << 16)); |
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/* burst time */ |
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*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x00f00000) | (7 << 20)); |
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/* tristate time */ |
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*CSR_SA110_CNTL = ((*CSR_SA110_CNTL & ~0x0f000000) | (7 << 24)); |
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} |
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return 0; |
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} |
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static void __exit cleanup_dc21285(void) |
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{ |
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mtd_device_unregister(dc21285_mtd); |
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map_destroy(dc21285_mtd); |
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iounmap(dc21285_map.virt); |
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} |
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module_init(init_dc21285); |
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module_exit(cleanup_dc21285); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Nicolas Pitre <[email protected]>"); |
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MODULE_DESCRIPTION("MTD map driver for DC21285 boards");
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