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124 lines
3.0 KiB
124 lines
3.0 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* SiFive FU540 Platform DMA driver |
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* Copyright (C) 2019 SiFive |
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* |
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* Based partially on: |
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* - drivers/dma/fsl-edma.c |
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* - drivers/dma/dw-edma/ |
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* - drivers/dma/pxa-dma.c |
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* |
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* See the following sources for further documentation: |
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* - Chapter 12 "Platform DMA Engine (PDMA)" of |
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* SiFive FU540-C000 v1.0 |
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* https://static.dev.sifive.com/FU540-C000-v1.0.pdf |
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*/ |
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#ifndef _SF_PDMA_H |
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#define _SF_PDMA_H |
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#include <linux/dmaengine.h> |
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#include <linux/dma-direction.h> |
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#include "../dmaengine.h" |
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#include "../virt-dma.h" |
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#define PDMA_NR_CH 4 |
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#if (PDMA_NR_CH != 4) |
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#error "Please define PDMA_NR_CH to 4" |
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#endif |
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#define PDMA_BASE_ADDR 0x3000000 |
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#define PDMA_CHAN_OFFSET 0x1000 |
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/* Register Offset */ |
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#define PDMA_CTRL 0x000 |
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#define PDMA_XFER_TYPE 0x004 |
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#define PDMA_XFER_SIZE 0x008 |
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#define PDMA_DST_ADDR 0x010 |
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#define PDMA_SRC_ADDR 0x018 |
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#define PDMA_ACT_TYPE 0x104 /* Read-only */ |
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#define PDMA_REMAINING_BYTE 0x108 /* Read-only */ |
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#define PDMA_CUR_DST_ADDR 0x110 /* Read-only*/ |
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#define PDMA_CUR_SRC_ADDR 0x118 /* Read-only*/ |
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/* CTRL */ |
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#define PDMA_CLEAR_CTRL 0x0 |
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#define PDMA_CLAIM_MASK GENMASK(0, 0) |
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#define PDMA_RUN_MASK GENMASK(1, 1) |
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#define PDMA_ENABLE_DONE_INT_MASK GENMASK(14, 14) |
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#define PDMA_ENABLE_ERR_INT_MASK GENMASK(15, 15) |
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#define PDMA_DONE_STATUS_MASK GENMASK(30, 30) |
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#define PDMA_ERR_STATUS_MASK GENMASK(31, 31) |
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/* Transfer Type */ |
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#define PDMA_FULL_SPEED 0xFF000008 |
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/* Error Recovery */ |
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#define MAX_RETRY 1 |
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#define SF_PDMA_REG_BASE(ch) (pdma->membase + (PDMA_CHAN_OFFSET * (ch))) |
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struct pdma_regs { |
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/* read-write regs */ |
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void __iomem *ctrl; /* 4 bytes */ |
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void __iomem *xfer_type; /* 4 bytes */ |
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void __iomem *xfer_size; /* 8 bytes */ |
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void __iomem *dst_addr; /* 8 bytes */ |
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void __iomem *src_addr; /* 8 bytes */ |
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/* read-only */ |
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void __iomem *act_type; /* 4 bytes */ |
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void __iomem *residue; /* 8 bytes */ |
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void __iomem *cur_dst_addr; /* 8 bytes */ |
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void __iomem *cur_src_addr; /* 8 bytes */ |
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}; |
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struct sf_pdma_desc { |
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u32 xfer_type; |
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u64 xfer_size; |
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u64 dst_addr; |
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u64 src_addr; |
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struct virt_dma_desc vdesc; |
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struct sf_pdma_chan *chan; |
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bool in_use; |
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enum dma_transfer_direction dirn; |
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struct dma_async_tx_descriptor *async_tx; |
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}; |
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enum sf_pdma_pm_state { |
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RUNNING = 0, |
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SUSPENDED, |
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}; |
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struct sf_pdma_chan { |
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struct virt_dma_chan vchan; |
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enum dma_status status; |
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enum sf_pdma_pm_state pm_state; |
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u32 slave_id; |
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struct sf_pdma *pdma; |
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struct sf_pdma_desc *desc; |
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struct dma_slave_config cfg; |
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u32 attr; |
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dma_addr_t dma_dev_addr; |
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u32 dma_dev_size; |
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struct tasklet_struct done_tasklet; |
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struct tasklet_struct err_tasklet; |
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struct pdma_regs regs; |
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spinlock_t lock; /* protect chan data */ |
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bool xfer_err; |
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int txirq; |
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int errirq; |
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int retries; |
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}; |
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struct sf_pdma { |
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struct dma_device dma_dev; |
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void __iomem *membase; |
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void __iomem *mappedbase; |
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u32 n_chans; |
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struct sf_pdma_chan chans[PDMA_NR_CH]; |
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}; |
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#endif /* _SF_PDMA_H */
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