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153 lines
4.5 KiB
153 lines
4.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright 2019 NXP */ |
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#ifndef __DPAA2_QDMA_H |
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#define __DPAA2_QDMA_H |
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#define DPAA2_QDMA_STORE_SIZE 16 |
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#define NUM_CH 8 |
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struct dpaa2_qdma_sd_d { |
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u32 rsv:32; |
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union { |
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struct { |
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u32 ssd:12; /* souce stride distance */ |
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u32 sss:12; /* souce stride size */ |
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u32 rsv1:8; |
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} sdf; |
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struct { |
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u32 dsd:12; /* Destination stride distance */ |
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u32 dss:12; /* Destination stride size */ |
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u32 rsv2:8; |
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} ddf; |
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} df; |
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u32 rbpcmd; /* Route-by-port command */ |
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u32 cmd; |
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} __attribute__((__packed__)); |
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/* Source descriptor command read transaction type for RBP=0: */ |
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/* coherent copy of cacheable memory */ |
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#define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28) |
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/* Destination descriptor command write transaction type for RBP=0: */ |
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/* coherent copy of cacheable memory */ |
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#define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28) |
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#define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28) |
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#define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */ |
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#define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */ |
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#define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */ |
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#define QMAN_FD_SL_DISABLE (0) /* short lengthe disabled */ |
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#define QMAN_FD_SL_ENABLE BIT(14) /* short lengthe enabled */ |
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#define QDMA_FINAL_BIT_DISABLE (0) /* final bit disable */ |
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#define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */ |
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#define QDMA_FD_SHORT_FORMAT BIT(11) /* short format */ |
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#define QDMA_FD_LONG_FORMAT (0) /* long format */ |
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#define QDMA_SER_DISABLE (8) /* no notification */ |
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#define QDMA_SER_CTX BIT(8) /* notification by FQD_CTX[fqid] */ |
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#define QDMA_SER_DEST (2 << 8) /* notification by destination desc */ |
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#define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */ |
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#define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */ |
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#define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */ |
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#define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */ |
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/* Flow Context: 49bit physical address */ |
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#define QMAN_FD_CBMT_ENABLE BIT(15) |
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#define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */ |
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#define QMAN_FD_SC_DISABLE (0) /* stashing control */ |
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#define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */ |
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#define QDMA_FL_FMT_SGE (0x2) /* Scatter gather frame */ |
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#define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */ |
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#define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */ |
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#define QDMA_FL_SL_LONG (0x0)/* long length */ |
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#define QDMA_FL_SL_SHORT (0x1) /* short length */ |
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#define QDMA_FL_F (0x1)/* last frame list bit */ |
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/*Description of Frame list table structure*/ |
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struct dpaa2_qdma_chan { |
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struct dpaa2_qdma_engine *qdma; |
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struct virt_dma_chan vchan; |
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struct virt_dma_desc vdesc; |
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enum dma_status status; |
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u32 fqid; |
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/* spinlock used by dpaa2 qdma driver */ |
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spinlock_t queue_lock; |
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struct dma_pool *fd_pool; |
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struct dma_pool *fl_pool; |
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struct dma_pool *sdd_pool; |
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struct list_head comp_used; |
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struct list_head comp_free; |
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}; |
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struct dpaa2_qdma_comp { |
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dma_addr_t fd_bus_addr; |
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dma_addr_t fl_bus_addr; |
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dma_addr_t desc_bus_addr; |
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struct dpaa2_fd *fd_virt_addr; |
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struct dpaa2_fl_entry *fl_virt_addr; |
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struct dpaa2_qdma_sd_d *desc_virt_addr; |
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struct dpaa2_qdma_chan *qchan; |
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struct virt_dma_desc vdesc; |
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struct list_head list; |
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}; |
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struct dpaa2_qdma_engine { |
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struct dma_device dma_dev; |
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u32 n_chans; |
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struct dpaa2_qdma_chan chans[NUM_CH]; |
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int qdma_wrtype_fixup; |
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int desc_allocated; |
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struct dpaa2_qdma_priv *priv; |
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}; |
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/* |
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* dpaa2_qdma_priv - driver private data |
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*/ |
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struct dpaa2_qdma_priv { |
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int dpqdma_id; |
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struct iommu_domain *iommu_domain; |
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struct dpdmai_attr dpdmai_attr; |
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struct device *dev; |
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struct fsl_mc_io *mc_io; |
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struct fsl_mc_device *dpdmai_dev; |
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u8 num_pairs; |
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struct dpaa2_qdma_engine *dpaa2_qdma; |
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struct dpaa2_qdma_priv_per_prio *ppriv; |
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struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM]; |
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u32 tx_fqid[DPDMAI_PRIO_NUM]; |
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}; |
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struct dpaa2_qdma_priv_per_prio { |
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int req_fqid; |
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int rsp_fqid; |
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int prio; |
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struct dpaa2_io_store *store; |
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struct dpaa2_io_notification_ctx nctx; |
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struct dpaa2_qdma_priv *priv; |
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}; |
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static struct soc_device_attribute soc_fixup_tuning[] = { |
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{ .family = "QorIQ LX2160A"}, |
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{ }, |
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}; |
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/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */ |
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#define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \ |
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sizeof(struct dpaa2_fl_entry) * 3 + \ |
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sizeof(struct dpaa2_qdma_sd_d) * 2) |
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static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma); |
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static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan, |
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struct list_head *head); |
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#endif /* __DPAA2_QDMA_H */
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