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435 lines
11 KiB
435 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* TI CPUFreq/OPP hw-supported driver |
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* |
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* Copyright (C) 2016-2017 Texas Instruments, Inc. |
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* Dave Gerlach <[email protected]> |
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*/ |
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#include <linux/cpu.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/pm_opp.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#define REVISION_MASK 0xF |
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#define REVISION_SHIFT 28 |
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#define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F |
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#define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA |
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#define DRA7_EFUSE_HAS_OD_MPU_OPP 11 |
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#define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15 |
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#define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18 |
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#define DRA7_EFUSE_HAS_ALL_MPU_OPP 23 |
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#define DRA76_EFUSE_HAS_ALL_MPU_OPP 24 |
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#define DRA7_EFUSE_NOM_MPU_OPP BIT(0) |
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#define DRA7_EFUSE_OD_MPU_OPP BIT(1) |
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#define DRA7_EFUSE_HIGH_MPU_OPP BIT(2) |
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#define DRA76_EFUSE_PLUS_MPU_OPP BIT(3) |
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#define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C |
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#define OMAP3_CONTROL_IDCODE 0x4830A204 |
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#define OMAP34xx_ProdID_SKUID 0x4830A20C |
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#define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270) |
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#define VERSION_COUNT 2 |
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struct ti_cpufreq_data; |
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struct ti_cpufreq_soc_data { |
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const char * const *reg_names; |
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unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data, |
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unsigned long efuse); |
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unsigned long efuse_fallback; |
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unsigned long efuse_offset; |
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unsigned long efuse_mask; |
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unsigned long efuse_shift; |
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unsigned long rev_offset; |
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bool multi_regulator; |
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}; |
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struct ti_cpufreq_data { |
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struct device *cpu_dev; |
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struct device_node *opp_node; |
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struct regmap *syscon; |
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const struct ti_cpufreq_soc_data *soc_data; |
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struct opp_table *opp_table; |
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}; |
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static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data, |
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unsigned long efuse) |
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{ |
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if (!efuse) |
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efuse = opp_data->soc_data->efuse_fallback; |
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/* AM335x and AM437x use "OPP disable" bits, so invert */ |
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return ~efuse; |
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} |
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static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data, |
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unsigned long efuse) |
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{ |
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unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP; |
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/* |
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* The efuse on dra7 and am57 parts contains a specific |
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* value indicating the highest available OPP. |
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*/ |
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switch (efuse) { |
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case DRA76_EFUSE_HAS_PLUS_MPU_OPP: |
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case DRA76_EFUSE_HAS_ALL_MPU_OPP: |
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calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP; |
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fallthrough; |
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case DRA7_EFUSE_HAS_ALL_MPU_OPP: |
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case DRA7_EFUSE_HAS_HIGH_MPU_OPP: |
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calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP; |
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fallthrough; |
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case DRA7_EFUSE_HAS_OD_MPU_OPP: |
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calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP; |
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} |
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return calculated_efuse; |
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} |
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static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data, |
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unsigned long efuse) |
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{ |
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/* OPP enable bit ("Speed Binned") */ |
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return BIT(efuse); |
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} |
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static struct ti_cpufreq_soc_data am3x_soc_data = { |
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.efuse_xlate = amx3_efuse_xlate, |
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.efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ, |
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.efuse_offset = 0x07fc, |
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.efuse_mask = 0x1fff, |
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.rev_offset = 0x600, |
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.multi_regulator = false, |
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}; |
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static struct ti_cpufreq_soc_data am4x_soc_data = { |
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.efuse_xlate = amx3_efuse_xlate, |
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.efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ, |
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.efuse_offset = 0x0610, |
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.efuse_mask = 0x3f, |
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.rev_offset = 0x600, |
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.multi_regulator = false, |
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}; |
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static struct ti_cpufreq_soc_data dra7_soc_data = { |
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.efuse_xlate = dra7_efuse_xlate, |
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.efuse_offset = 0x020c, |
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.efuse_mask = 0xf80000, |
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.efuse_shift = 19, |
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.rev_offset = 0x204, |
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.multi_regulator = true, |
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}; |
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/* |
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* OMAP35x TRM (SPRUF98K): |
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* CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. |
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* Control OMAP Status Register 15:0 (Address 0x4800 244C) |
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* to separate between omap3503, omap3515, omap3525, omap3530 |
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* and feature presence. |
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* There are encodings for versions limited to 400/266MHz |
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* but we ignore. |
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* Not clear if this also holds for omap34xx. |
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* some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1 |
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* are stored in the SYSCON register range |
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* Register 0x4830A20C [ProdID.SKUID] [0:3] |
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* 0x0 for normal 600/430MHz device. |
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* 0x8 for 720/520MHz device. |
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* Not clear what omap34xx value is. |
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*/ |
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static struct ti_cpufreq_soc_data omap34xx_soc_data = { |
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.efuse_xlate = omap3_efuse_xlate, |
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.efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE, |
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.efuse_shift = 3, |
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.efuse_mask = BIT(3), |
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.rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, |
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.multi_regulator = false, |
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}; |
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/* |
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* AM/DM37x TRM (SPRUGN4M) |
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* CONTROL_IDCODE (0x4830 A204) describes Silicon revisions. |
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* Control Device Status Register 15:0 (Address 0x4800 244C) |
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* to separate between am3703, am3715, dm3725, dm3730 |
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* and feature presence. |
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* Speed Binned = Bit 9 |
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* 0 800/600 MHz |
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* 1 1000/800 MHz |
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* some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1 |
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* are stored in the SYSCON register range. |
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* There is no 0x4830A20C [ProdID.SKUID] register (exists but |
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* seems to always read as 0). |
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*/ |
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static const char * const omap3_reg_names[] = {"cpu0", "vbb"}; |
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static struct ti_cpufreq_soc_data omap36xx_soc_data = { |
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.reg_names = omap3_reg_names, |
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.efuse_xlate = omap3_efuse_xlate, |
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.efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE, |
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.efuse_shift = 9, |
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.efuse_mask = BIT(9), |
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.rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, |
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.multi_regulator = true, |
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}; |
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/* |
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* AM3517 is quite similar to AM/DM37x except that it has no |
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* high speed grade eFuse and no abb ldo |
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*/ |
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static struct ti_cpufreq_soc_data am3517_soc_data = { |
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.efuse_xlate = omap3_efuse_xlate, |
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.efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE, |
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.efuse_shift = 0, |
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.efuse_mask = 0, |
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.rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE, |
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.multi_regulator = false, |
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}; |
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/** |
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* ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC |
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* @opp_data: pointer to ti_cpufreq_data context |
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* @efuse_value: Set to the value parsed from efuse |
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* |
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* Returns error code if efuse not read properly. |
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*/ |
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static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, |
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u32 *efuse_value) |
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{ |
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struct device *dev = opp_data->cpu_dev; |
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u32 efuse; |
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int ret; |
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ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, |
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&efuse); |
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if (ret == -EIO) { |
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/* not a syscon register! */ |
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void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + |
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opp_data->soc_data->efuse_offset, 4); |
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if (!regs) |
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return -ENOMEM; |
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efuse = readl(regs); |
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iounmap(regs); |
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} |
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else if (ret) { |
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dev_err(dev, |
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"Failed to read the efuse value from syscon: %d\n", |
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ret); |
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return ret; |
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} |
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efuse = (efuse & opp_data->soc_data->efuse_mask); |
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efuse >>= opp_data->soc_data->efuse_shift; |
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*efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse); |
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return 0; |
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} |
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/** |
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* ti_cpufreq_get_rev() - Parse and return rev value present on SoC |
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* @opp_data: pointer to ti_cpufreq_data context |
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* @revision_value: Set to the value parsed from revision register |
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* |
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* Returns error code if revision not read properly. |
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*/ |
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static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, |
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u32 *revision_value) |
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{ |
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struct device *dev = opp_data->cpu_dev; |
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u32 revision; |
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int ret; |
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ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, |
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&revision); |
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if (ret == -EIO) { |
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/* not a syscon register! */ |
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void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + |
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opp_data->soc_data->rev_offset, 4); |
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if (!regs) |
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return -ENOMEM; |
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revision = readl(regs); |
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iounmap(regs); |
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} |
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else if (ret) { |
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dev_err(dev, |
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"Failed to read the revision number from syscon: %d\n", |
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ret); |
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return ret; |
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} |
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*revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK); |
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return 0; |
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} |
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static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data) |
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{ |
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struct device *dev = opp_data->cpu_dev; |
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struct device_node *np = opp_data->opp_node; |
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opp_data->syscon = syscon_regmap_lookup_by_phandle(np, |
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"syscon"); |
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if (IS_ERR(opp_data->syscon)) { |
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dev_err(dev, |
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"\"syscon\" is missing, cannot use OPPv2 table.\n"); |
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return PTR_ERR(opp_data->syscon); |
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} |
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return 0; |
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} |
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static const struct of_device_id ti_cpufreq_of_match[] = { |
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{ .compatible = "ti,am33xx", .data = &am3x_soc_data, }, |
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{ .compatible = "ti,am3517", .data = &am3517_soc_data, }, |
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{ .compatible = "ti,am43", .data = &am4x_soc_data, }, |
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{ .compatible = "ti,dra7", .data = &dra7_soc_data }, |
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{ .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, }, |
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{ .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, }, |
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/* legacy */ |
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{ .compatible = "ti,omap3430", .data = &omap34xx_soc_data, }, |
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{ .compatible = "ti,omap3630", .data = &omap36xx_soc_data, }, |
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{}, |
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}; |
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static const struct of_device_id *ti_cpufreq_match_node(void) |
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{ |
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struct device_node *np; |
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const struct of_device_id *match; |
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np = of_find_node_by_path("/"); |
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match = of_match_node(ti_cpufreq_of_match, np); |
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of_node_put(np); |
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return match; |
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} |
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static int ti_cpufreq_probe(struct platform_device *pdev) |
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{ |
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u32 version[VERSION_COUNT]; |
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const struct of_device_id *match; |
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struct opp_table *ti_opp_table; |
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struct ti_cpufreq_data *opp_data; |
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const char * const default_reg_names[] = {"vdd", "vbb"}; |
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int ret; |
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match = dev_get_platdata(&pdev->dev); |
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if (!match) |
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return -ENODEV; |
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opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL); |
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if (!opp_data) |
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return -ENOMEM; |
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opp_data->soc_data = match->data; |
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opp_data->cpu_dev = get_cpu_device(0); |
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if (!opp_data->cpu_dev) { |
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pr_err("%s: Failed to get device for CPU0\n", __func__); |
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return -ENODEV; |
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} |
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opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev); |
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if (!opp_data->opp_node) { |
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dev_info(opp_data->cpu_dev, |
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"OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n"); |
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goto register_cpufreq_dt; |
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} |
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ret = ti_cpufreq_setup_syscon_register(opp_data); |
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if (ret) |
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goto fail_put_node; |
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/* |
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* OPPs determine whether or not they are supported based on |
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* two metrics: |
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* 0 - SoC Revision |
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* 1 - eFuse value |
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*/ |
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ret = ti_cpufreq_get_rev(opp_data, &version[0]); |
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if (ret) |
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goto fail_put_node; |
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ret = ti_cpufreq_get_efuse(opp_data, &version[1]); |
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if (ret) |
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goto fail_put_node; |
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ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev, |
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version, VERSION_COUNT); |
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if (IS_ERR(ti_opp_table)) { |
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dev_err(opp_data->cpu_dev, |
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"Failed to set supported hardware\n"); |
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ret = PTR_ERR(ti_opp_table); |
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goto fail_put_node; |
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} |
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opp_data->opp_table = ti_opp_table; |
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if (opp_data->soc_data->multi_regulator) { |
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const char * const *reg_names = default_reg_names; |
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if (opp_data->soc_data->reg_names) |
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reg_names = opp_data->soc_data->reg_names; |
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ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev, |
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reg_names, |
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ARRAY_SIZE(default_reg_names)); |
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if (IS_ERR(ti_opp_table)) { |
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dev_pm_opp_put_supported_hw(opp_data->opp_table); |
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ret = PTR_ERR(ti_opp_table); |
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goto fail_put_node; |
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} |
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} |
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of_node_put(opp_data->opp_node); |
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register_cpufreq_dt: |
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platform_device_register_simple("cpufreq-dt", -1, NULL, 0); |
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return 0; |
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fail_put_node: |
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of_node_put(opp_data->opp_node); |
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return ret; |
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} |
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static int ti_cpufreq_init(void) |
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{ |
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const struct of_device_id *match; |
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/* Check to ensure we are on a compatible platform */ |
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match = ti_cpufreq_match_node(); |
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if (match) |
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platform_device_register_data(NULL, "ti-cpufreq", -1, match, |
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sizeof(*match)); |
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return 0; |
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} |
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module_init(ti_cpufreq_init); |
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static struct platform_driver ti_cpufreq_driver = { |
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.probe = ti_cpufreq_probe, |
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.driver = { |
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.name = "ti-cpufreq", |
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}, |
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}; |
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builtin_platform_driver(ti_cpufreq_driver); |
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MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver"); |
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MODULE_AUTHOR("Dave Gerlach <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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