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319 lines
7.4 KiB
319 lines
7.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2006-2009 Simtec Electronics |
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* http://armlinux.simtec.co.uk/ |
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* Ben Dooks <[email protected]> |
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* Vincent Sanders <[email protected]> |
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* |
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* S3C2440/S3C2442 CPU Frequency scaling |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <linux/cpufreq.h> |
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#include <linux/device.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/soc/samsung/s3c-cpufreq-core.h> |
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#include <linux/soc/samsung/s3c-pm.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#define S3C2440_CLKDIVN_PDIVN (1<<0) |
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#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) |
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#define S3C2440_CLKDIVN_HDIVN_1 (0<<1) |
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#define S3C2440_CLKDIVN_HDIVN_2 (1<<1) |
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#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) |
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#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) |
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#define S3C2440_CLKDIVN_UCLK (1<<3) |
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#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) |
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#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) |
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#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) |
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#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) |
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#define S3C2440_CAMDIVN_DVSEN (1<<12) |
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#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5) |
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static struct clk *xtal; |
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static struct clk *fclk; |
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static struct clk *hclk; |
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static struct clk *armclk; |
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/* HDIV: 1, 2, 3, 4, 6, 8 */ |
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static inline int within_khz(unsigned long a, unsigned long b) |
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{ |
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long diff = a - b; |
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return (diff >= -1000 && diff <= 1000); |
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} |
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/** |
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* s3c2440_cpufreq_calcdivs - calculate divider settings |
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* @cfg: The cpu frequency settings. |
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* |
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* Calcualte the divider values for the given frequency settings |
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* specified in @cfg. The values are stored in @cfg for later use |
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* by the relevant set routine if the request settings can be reached. |
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*/ |
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static int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) |
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{ |
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unsigned int hdiv, pdiv; |
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unsigned long hclk, fclk, armclk; |
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unsigned long hclk_max; |
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fclk = cfg->freq.fclk; |
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armclk = cfg->freq.armclk; |
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hclk_max = cfg->max.hclk; |
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s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", |
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__func__, fclk, armclk, hclk_max); |
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if (armclk > fclk) { |
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pr_warn("%s: armclk > fclk\n", __func__); |
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armclk = fclk; |
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} |
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/* if we are in DVS, we need HCLK to be <= ARMCLK */ |
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if (armclk < fclk && armclk < hclk_max) |
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hclk_max = armclk; |
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for (hdiv = 1; hdiv < 9; hdiv++) { |
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if (hdiv == 5 || hdiv == 7) |
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hdiv++; |
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hclk = (fclk / hdiv); |
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if (hclk <= hclk_max || within_khz(hclk, hclk_max)) |
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break; |
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} |
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s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv); |
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if (hdiv > 8) |
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goto invalid; |
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pdiv = (hclk > cfg->max.pclk) ? 2 : 1; |
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if ((hclk / pdiv) > cfg->max.pclk) |
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pdiv++; |
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s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); |
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if (pdiv > 2) |
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goto invalid; |
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pdiv *= hdiv; |
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/* calculate a valid armclk */ |
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if (armclk < hclk) |
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armclk = hclk; |
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/* if we're running armclk lower than fclk, this really means |
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* that the system should go into dvs mode, which means that |
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* armclk is connected to hclk. */ |
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if (armclk < fclk) { |
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cfg->divs.dvs = 1; |
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armclk = hclk; |
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} else |
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cfg->divs.dvs = 0; |
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cfg->freq.armclk = armclk; |
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/* store the result, and then return */ |
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cfg->divs.h_divisor = hdiv; |
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cfg->divs.p_divisor = pdiv; |
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return 0; |
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invalid: |
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return -EINVAL; |
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} |
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#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \ |
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S3C2440_CAMDIVN_HCLK4_HALF) |
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/** |
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* s3c2440_cpufreq_setdivs - set the cpu frequency divider settings |
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* @cfg: The cpu frequency settings. |
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* |
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* Set the divisors from the settings in @cfg, which where generated |
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* during the calculation phase by s3c2440_cpufreq_calcdivs(). |
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*/ |
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static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) |
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{ |
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unsigned long clkdiv, camdiv; |
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s3c_freq_dbg("%s: divisors: h=%d, p=%d\n", __func__, |
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cfg->divs.h_divisor, cfg->divs.p_divisor); |
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clkdiv = s3c24xx_read_clkdivn(); |
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camdiv = s3c2440_read_camdivn(); |
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clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN); |
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camdiv &= ~CAMDIVN_HCLK_HALF; |
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switch (cfg->divs.h_divisor) { |
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case 1: |
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clkdiv |= S3C2440_CLKDIVN_HDIVN_1; |
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break; |
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case 2: |
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clkdiv |= S3C2440_CLKDIVN_HDIVN_2; |
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break; |
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case 6: |
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camdiv |= S3C2440_CAMDIVN_HCLK3_HALF; |
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case 3: |
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clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6; |
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break; |
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case 8: |
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camdiv |= S3C2440_CAMDIVN_HCLK4_HALF; |
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case 4: |
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clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8; |
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break; |
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default: |
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BUG(); /* we don't expect to get here. */ |
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} |
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if (cfg->divs.p_divisor != cfg->divs.h_divisor) |
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clkdiv |= S3C2440_CLKDIVN_PDIVN; |
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/* todo - set pclk. */ |
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/* Write the divisors first with hclk intentionally halved so that |
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* when we write clkdiv we will under-frequency instead of over. We |
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* then make a short delay and remove the hclk halving if necessary. |
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*/ |
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s3c2440_write_camdivn(camdiv | CAMDIVN_HCLK_HALF); |
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s3c24xx_write_clkdivn(clkdiv); |
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ndelay(20); |
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s3c2440_write_camdivn(camdiv); |
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clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); |
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} |
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static int run_freq_for(unsigned long max_hclk, unsigned long fclk, |
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int *divs, |
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struct cpufreq_frequency_table *table, |
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size_t table_size) |
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{ |
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unsigned long freq; |
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int index = 0; |
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int div; |
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for (div = *divs; div > 0; div = *divs++) { |
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freq = fclk / div; |
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if (freq > max_hclk && div != 1) |
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continue; |
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freq /= 1000; /* table is in kHz */ |
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index = s3c_cpufreq_addfreq(table, index, table_size, freq); |
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if (index < 0) |
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break; |
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} |
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return index; |
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} |
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static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 }; |
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static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg, |
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struct cpufreq_frequency_table *table, |
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size_t table_size) |
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{ |
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int ret; |
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WARN_ON(cfg->info == NULL); |
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WARN_ON(cfg->board == NULL); |
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ret = run_freq_for(cfg->info->max.hclk, |
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cfg->info->max.fclk, |
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hclk_divs, |
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table, table_size); |
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s3c_freq_dbg("%s: returning %d\n", __func__, ret); |
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return ret; |
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} |
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static struct s3c_cpufreq_info s3c2440_cpufreq_info = { |
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.max = { |
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.fclk = 400000000, |
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.hclk = 133333333, |
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.pclk = 66666666, |
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}, |
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.locktime_m = 300, |
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.locktime_u = 300, |
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.locktime_bits = 16, |
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.name = "s3c244x", |
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.calc_iotiming = s3c2410_iotiming_calc, |
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.set_iotiming = s3c2410_iotiming_set, |
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.get_iotiming = s3c2410_iotiming_get, |
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.set_fvco = s3c2410_set_fvco, |
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.set_refresh = s3c2410_cpufreq_setrefresh, |
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.set_divs = s3c2440_cpufreq_setdivs, |
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.calc_divs = s3c2440_cpufreq_calcdivs, |
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.calc_freqtable = s3c2440_cpufreq_calctable, |
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.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), |
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}; |
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static int s3c2440_cpufreq_add(struct device *dev, |
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struct subsys_interface *sif) |
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{ |
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xtal = s3c_cpufreq_clk_get(NULL, "xtal"); |
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hclk = s3c_cpufreq_clk_get(NULL, "hclk"); |
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fclk = s3c_cpufreq_clk_get(NULL, "fclk"); |
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armclk = s3c_cpufreq_clk_get(NULL, "armclk"); |
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if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) { |
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pr_err("%s: failed to get clocks\n", __func__); |
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return -ENOENT; |
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} |
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return s3c_cpufreq_register(&s3c2440_cpufreq_info); |
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} |
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static struct subsys_interface s3c2440_cpufreq_interface = { |
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.name = "s3c2440_cpufreq", |
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.subsys = &s3c2440_subsys, |
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.add_dev = s3c2440_cpufreq_add, |
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}; |
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static int s3c2440_cpufreq_init(void) |
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{ |
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return subsys_interface_register(&s3c2440_cpufreq_interface); |
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} |
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/* arch_initcall adds the clocks we need, so use subsys_initcall. */ |
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subsys_initcall(s3c2440_cpufreq_init); |
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static struct subsys_interface s3c2442_cpufreq_interface = { |
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.name = "s3c2442_cpufreq", |
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.subsys = &s3c2442_subsys, |
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.add_dev = s3c2440_cpufreq_add, |
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}; |
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static int s3c2442_cpufreq_init(void) |
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{ |
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return subsys_interface_register(&s3c2442_cpufreq_interface); |
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} |
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subsys_initcall(s3c2442_cpufreq_init);
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