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215 lines
8.5 KiB
215 lines
8.5 KiB
.. SPDX-License-Identifier: GPL-2.0 |
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.. include:: <isonum.txt> |
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====================================================== |
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Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop) |
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====================================================== |
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Controller Register Map |
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----------------------- |
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For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2 |
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============== ================================== |
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BAR0 offset Register |
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============== ================================== |
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0x11C5C Link Interface IRQ Set |
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0x11C60 Link Interface IRQ Clear |
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============== ================================== |
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============== ================================== |
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BAR2 offset Register |
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============== ================================== |
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0x10 Inbound Message Register 0 |
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0x14 Inbound Message Register 1 |
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0x18 Outbound Message Register 0 |
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0x1C Outbound Message Register 1 |
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0x20 Inbound Doorbell Register |
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0x24 Inbound Interrupt Status Register |
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0x28 Inbound Interrupt Mask Register |
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0x30 Outbound Interrupt Status Register |
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0x34 Outbound Interrupt Mask Register |
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0x40 Inbound Queue Port |
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0x44 Outbound Queue Port |
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============== ================================== |
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For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0: |
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============== ================================== |
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BAR0 offset Register |
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============== ================================== |
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0x10 Inbound Message Register 0 |
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0x14 Inbound Message Register 1 |
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0x18 Outbound Message Register 0 |
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0x1C Outbound Message Register 1 |
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0x20 Inbound Doorbell Register |
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0x24 Inbound Interrupt Status Register |
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0x28 Inbound Interrupt Mask Register |
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0x30 Outbound Interrupt Status Register |
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0x34 Outbound Interrupt Mask Register |
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0x40 Inbound Queue Port |
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0x44 Outbound Queue Port |
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============== ================================== |
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For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: |
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============== ================================== |
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BAR0 offset Register |
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============== ================================== |
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0x20400 Inbound Doorbell Register |
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0x20404 Inbound Interrupt Mask Register |
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0x20408 Outbound Doorbell Register |
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0x2040C Outbound Interrupt Mask Register |
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============== ================================== |
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============== ================================== |
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BAR1 offset Register |
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============== ================================== |
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0x0 Inbound Queue Head Pointer |
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0x4 Inbound Queue Tail Pointer |
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0x8 Outbound Queue Head Pointer |
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0xC Outbound Queue Tail Pointer |
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0x10 Inbound Message Register |
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0x14 Outbound Message Register |
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0x40-0x1040 Inbound Queue |
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0x1040-0x2040 Outbound Queue |
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============== ================================== |
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For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1: |
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============== ================================== |
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BAR0 offset Register |
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============== ================================== |
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0x0 IOP configuration information. |
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============== ================================== |
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============== =================================================== |
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BAR1 offset Register |
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============== =================================================== |
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0x4000 Inbound List Base Address Low |
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0x4004 Inbound List Base Address High |
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0x4018 Inbound List Write Pointer |
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0x402C Inbound List Configuration and Control |
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0x4050 Outbound List Base Address Low |
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0x4054 Outbound List Base Address High |
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0x4058 Outbound List Copy Pointer Shadow Base Address Low |
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0x405C Outbound List Copy Pointer Shadow Base Address High |
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0x4088 Outbound List Interrupt Cause |
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0x408C Outbound List Interrupt Enable |
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0x1020C PCIe Function 0 Interrupt Enable |
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0x10400 PCIe Function 0 to CPU Message A |
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0x10420 CPU to PCIe Function 0 Message A |
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0x10480 CPU to PCIe Function 0 Doorbell |
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0x10484 CPU to PCIe Function 0 Doorbell Enable |
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============== =================================================== |
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I/O Request Workflow of Not Marvell Frey |
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---------------------------------------- |
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All queued requests are handled via inbound/outbound queue port. |
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A request packet can be allocated in either IOP or host memory. |
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To send a request to the controller: |
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- Get a free request packet by reading the inbound queue port or |
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allocate a free request in host DMA coherent memory. |
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The value returned from the inbound queue port is an offset |
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relative to the IOP BAR0. |
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Requests allocated in host memory must be aligned on 32-bytes boundary. |
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- Fill the packet. |
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- Post the packet to IOP by writing it to inbound queue. For requests |
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allocated in IOP memory, write the offset to inbound queue port. For |
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requests allocated in host memory, write (0x80000000|(bus_addr>>5)) |
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to the inbound queue port. |
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- The IOP process the request. When the request is completed, it |
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will be put into outbound queue. An outbound interrupt will be |
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generated. |
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For requests allocated in IOP memory, the request offset is posted to |
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outbound queue. |
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For requests allocated in host memory, (0x80000000|(bus_addr>>5)) |
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is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT |
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flag is set in the request, the low 32-bit context value will be |
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posted instead. |
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- The host read the outbound queue and complete the request. |
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For requests allocated in IOP memory, the host driver free the request |
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by writing it to the outbound queue. |
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Non-queued requests (reset/flush etc) can be sent via inbound message |
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register 0. An outbound message with the same value indicates the completion |
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of an inbound message. |
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I/O Request Workflow of Marvell Frey |
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------------------------------------ |
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All queued requests are handled via inbound/outbound list. |
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To send a request to the controller: |
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- Allocate a free request in host DMA coherent memory. |
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Requests allocated in host memory must be aligned on 32-bytes boundary. |
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- Fill the request with index of the request in the flag. |
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Fill a free inbound list unit with the physical address and the size of |
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the request. |
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Set up the inbound list write pointer with the index of previous unit, |
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round to 0 if the index reaches the supported count of requests. |
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- Post the inbound list writer pointer to IOP. |
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- The IOP process the request. When the request is completed, the flag of |
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the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a |
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free outbound list unit and the index of the outbound list unit will be |
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put into the copy pointer shadow register. An outbound interrupt will be |
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generated. |
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- The host read the outbound list copy pointer shadow register and compare |
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with previous saved read pointer N. If they are different, the host will |
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read the (N+1)th outbound list unit. |
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The host get the index of the request from the (N+1)th outbound list |
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unit and complete the request. |
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Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe |
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Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register |
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with the same value indicates the completion of message. |
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User-level Interface |
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--------------------- |
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The driver exposes following sysfs attributes: |
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================== === ======================== |
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NAME R/W Description |
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================== === ======================== |
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driver-version R driver version string |
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firmware-version R firmware version string |
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================== === ======================== |
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----------------------------------------------------------------------------- |
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Copyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved. |
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This file is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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[email protected] |
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http://www.highpoint-tech.com
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