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679 lines
16 KiB
679 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// ALSA Soc Audio Layer - I2S core for newer Samsung SoCs. |
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// |
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// Copyright (c) 2006 Wolfson Microelectronics PLC. |
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// Graeme Gregory [email protected] |
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// [email protected] |
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// |
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// Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics |
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// http://armlinux.simtec.co.uk/ |
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// Ben Dooks <[email protected]> |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <sound/soc.h> |
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#include <sound/pcm_params.h> |
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#include "regs-i2s-v2.h" |
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#include "s3c-i2s-v2.h" |
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#undef S3C_IIS_V2_SUPPORTED |
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#if defined(CONFIG_CPU_S3C2412) \ |
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|| defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_CPU_S5PV210) |
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#define S3C_IIS_V2_SUPPORTED |
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#endif |
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#ifndef S3C_IIS_V2_SUPPORTED |
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#error Unsupported CPU model |
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#endif |
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#define S3C2412_I2S_DEBUG_CON 0 |
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static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai) |
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{ |
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return snd_soc_dai_get_drvdata(cpu_dai); |
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} |
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#define bit_set(v, b) (((v) & (b)) ? 1 : 0) |
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#if S3C2412_I2S_DEBUG_CON |
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static void dbg_showcon(const char *fn, u32 con) |
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{ |
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printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn, |
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bit_set(con, S3C2412_IISCON_LRINDEX), |
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bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY), |
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bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY), |
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bit_set(con, S3C2412_IISCON_TXFIFO_FULL), |
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bit_set(con, S3C2412_IISCON_RXFIFO_FULL)); |
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printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n", |
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fn, |
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bit_set(con, S3C2412_IISCON_TXDMA_PAUSE), |
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bit_set(con, S3C2412_IISCON_RXDMA_PAUSE), |
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bit_set(con, S3C2412_IISCON_TXCH_PAUSE), |
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bit_set(con, S3C2412_IISCON_RXCH_PAUSE)); |
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printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn, |
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bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE), |
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bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE), |
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bit_set(con, S3C2412_IISCON_IIS_ACTIVE)); |
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} |
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#else |
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static inline void dbg_showcon(const char *fn, u32 con) |
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{ |
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} |
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#endif |
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/* Turn on or off the transmission path. */ |
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static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on) |
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{ |
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void __iomem *regs = i2s->regs; |
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u32 fic, con, mod; |
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pr_debug("%s(%d)\n", __func__, on); |
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fic = readl(regs + S3C2412_IISFIC); |
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con = readl(regs + S3C2412_IISCON); |
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mod = readl(regs + S3C2412_IISMOD); |
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pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
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if (on) { |
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con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE; |
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con &= ~S3C2412_IISCON_TXDMA_PAUSE; |
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con &= ~S3C2412_IISCON_TXCH_PAUSE; |
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switch (mod & S3C2412_IISMOD_MODE_MASK) { |
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case S3C2412_IISMOD_MODE_TXONLY: |
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case S3C2412_IISMOD_MODE_TXRX: |
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/* do nothing, we are in the right mode */ |
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break; |
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case S3C2412_IISMOD_MODE_RXONLY: |
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mod &= ~S3C2412_IISMOD_MODE_MASK; |
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mod |= S3C2412_IISMOD_MODE_TXRX; |
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break; |
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default: |
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dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n", |
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mod & S3C2412_IISMOD_MODE_MASK); |
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break; |
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} |
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writel(con, regs + S3C2412_IISCON); |
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writel(mod, regs + S3C2412_IISMOD); |
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} else { |
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/* Note, we do not have any indication that the FIFO problems |
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* tha the S3C2410/2440 had apply here, so we should be able |
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* to disable the DMA and TX without resetting the FIFOS. |
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*/ |
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con |= S3C2412_IISCON_TXDMA_PAUSE; |
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con |= S3C2412_IISCON_TXCH_PAUSE; |
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con &= ~S3C2412_IISCON_TXDMA_ACTIVE; |
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switch (mod & S3C2412_IISMOD_MODE_MASK) { |
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case S3C2412_IISMOD_MODE_TXRX: |
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mod &= ~S3C2412_IISMOD_MODE_MASK; |
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mod |= S3C2412_IISMOD_MODE_RXONLY; |
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break; |
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case S3C2412_IISMOD_MODE_TXONLY: |
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mod &= ~S3C2412_IISMOD_MODE_MASK; |
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con &= ~S3C2412_IISCON_IIS_ACTIVE; |
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break; |
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default: |
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dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n", |
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mod & S3C2412_IISMOD_MODE_MASK); |
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break; |
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} |
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writel(mod, regs + S3C2412_IISMOD); |
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writel(con, regs + S3C2412_IISCON); |
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} |
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fic = readl(regs + S3C2412_IISFIC); |
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dbg_showcon(__func__, con); |
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pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
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} |
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static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on) |
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{ |
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void __iomem *regs = i2s->regs; |
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u32 fic, con, mod; |
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pr_debug("%s(%d)\n", __func__, on); |
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fic = readl(regs + S3C2412_IISFIC); |
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con = readl(regs + S3C2412_IISCON); |
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mod = readl(regs + S3C2412_IISMOD); |
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pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
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if (on) { |
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con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE; |
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con &= ~S3C2412_IISCON_RXDMA_PAUSE; |
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con &= ~S3C2412_IISCON_RXCH_PAUSE; |
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switch (mod & S3C2412_IISMOD_MODE_MASK) { |
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case S3C2412_IISMOD_MODE_TXRX: |
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case S3C2412_IISMOD_MODE_RXONLY: |
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/* do nothing, we are in the right mode */ |
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break; |
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case S3C2412_IISMOD_MODE_TXONLY: |
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mod &= ~S3C2412_IISMOD_MODE_MASK; |
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mod |= S3C2412_IISMOD_MODE_TXRX; |
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break; |
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default: |
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dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n", |
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mod & S3C2412_IISMOD_MODE_MASK); |
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} |
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writel(mod, regs + S3C2412_IISMOD); |
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writel(con, regs + S3C2412_IISCON); |
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} else { |
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/* See txctrl notes on FIFOs. */ |
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con &= ~S3C2412_IISCON_RXDMA_ACTIVE; |
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con |= S3C2412_IISCON_RXDMA_PAUSE; |
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con |= S3C2412_IISCON_RXCH_PAUSE; |
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switch (mod & S3C2412_IISMOD_MODE_MASK) { |
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case S3C2412_IISMOD_MODE_RXONLY: |
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con &= ~S3C2412_IISCON_IIS_ACTIVE; |
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mod &= ~S3C2412_IISMOD_MODE_MASK; |
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break; |
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case S3C2412_IISMOD_MODE_TXRX: |
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mod &= ~S3C2412_IISMOD_MODE_MASK; |
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mod |= S3C2412_IISMOD_MODE_TXONLY; |
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break; |
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default: |
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dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n", |
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mod & S3C2412_IISMOD_MODE_MASK); |
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} |
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writel(con, regs + S3C2412_IISCON); |
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writel(mod, regs + S3C2412_IISMOD); |
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} |
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fic = readl(regs + S3C2412_IISFIC); |
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pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic); |
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} |
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#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
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/* |
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* Wait for the LR signal to allow synchronisation to the L/R clock |
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* from the codec. May only be needed for slave mode. |
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*/ |
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static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s) |
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{ |
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u32 iiscon; |
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unsigned long loops = msecs_to_loops(5); |
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pr_debug("Entered %s\n", __func__); |
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while (--loops) { |
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iiscon = readl(i2s->regs + S3C2412_IISCON); |
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if (iiscon & S3C2412_IISCON_LRINDEX) |
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break; |
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cpu_relax(); |
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} |
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if (!loops) { |
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printk(KERN_ERR "%s: timeout\n", __func__); |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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/* |
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* Set S3C2412 I2S DAI format |
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*/ |
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static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai, |
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unsigned int fmt) |
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{ |
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struct s3c_i2sv2_info *i2s = to_info(cpu_dai); |
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u32 iismod; |
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pr_debug("Entered %s\n", __func__); |
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iismod = readl(i2s->regs + S3C2412_IISMOD); |
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pr_debug("hw_params r: IISMOD: %x \n", iismod); |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBM_CFM: |
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i2s->master = 0; |
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iismod |= S3C2412_IISMOD_SLAVE; |
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break; |
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case SND_SOC_DAIFMT_CBS_CFS: |
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i2s->master = 1; |
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iismod &= ~S3C2412_IISMOD_SLAVE; |
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break; |
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default: |
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pr_err("unknown master/slave format\n"); |
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return -EINVAL; |
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} |
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iismod &= ~S3C2412_IISMOD_SDF_MASK; |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_RIGHT_J: |
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iismod |= S3C2412_IISMOD_LR_RLOW; |
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iismod |= S3C2412_IISMOD_SDF_MSB; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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iismod |= S3C2412_IISMOD_LR_RLOW; |
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iismod |= S3C2412_IISMOD_SDF_LSB; |
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break; |
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case SND_SOC_DAIFMT_I2S: |
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iismod &= ~S3C2412_IISMOD_LR_RLOW; |
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iismod |= S3C2412_IISMOD_SDF_IIS; |
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break; |
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default: |
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pr_err("Unknown data format\n"); |
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return -EINVAL; |
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} |
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writel(iismod, i2s->regs + S3C2412_IISMOD); |
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pr_debug("hw_params w: IISMOD: %x \n", iismod); |
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return 0; |
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} |
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static int s3c_i2sv2_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct s3c_i2sv2_info *i2s = to_info(dai); |
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struct snd_dmaengine_dai_dma_data *dma_data; |
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u32 iismod; |
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pr_debug("Entered %s\n", __func__); |
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
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dma_data = i2s->dma_playback; |
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else |
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dma_data = i2s->dma_capture; |
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snd_soc_dai_set_dma_data(dai, substream, dma_data); |
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/* Working copies of register */ |
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iismod = readl(i2s->regs + S3C2412_IISMOD); |
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pr_debug("%s: r: IISMOD: %x\n", __func__, iismod); |
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iismod &= ~S3C64XX_IISMOD_BLC_MASK; |
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/* Sample size */ |
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switch (params_width(params)) { |
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case 8: |
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iismod |= S3C64XX_IISMOD_BLC_8BIT; |
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break; |
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case 16: |
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break; |
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case 24: |
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iismod |= S3C64XX_IISMOD_BLC_24BIT; |
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break; |
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} |
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writel(iismod, i2s->regs + S3C2412_IISMOD); |
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pr_debug("%s: w: IISMOD: %x\n", __func__, iismod); |
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return 0; |
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} |
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static int s3c_i2sv2_set_sysclk(struct snd_soc_dai *cpu_dai, |
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int clk_id, unsigned int freq, int dir) |
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{ |
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struct s3c_i2sv2_info *i2s = to_info(cpu_dai); |
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u32 iismod = readl(i2s->regs + S3C2412_IISMOD); |
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pr_debug("Entered %s\n", __func__); |
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pr_debug("%s r: IISMOD: %x\n", __func__, iismod); |
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switch (clk_id) { |
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case S3C_I2SV2_CLKSRC_PCLK: |
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iismod &= ~S3C2412_IISMOD_IMS_SYSMUX; |
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break; |
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case S3C_I2SV2_CLKSRC_AUDIOBUS: |
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iismod |= S3C2412_IISMOD_IMS_SYSMUX; |
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break; |
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case S3C_I2SV2_CLKSRC_CDCLK: |
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/* Error if controller doesn't have the CDCLKCON bit */ |
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if (!(i2s->feature & S3C_FEATURE_CDCLKCON)) |
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return -EINVAL; |
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switch (dir) { |
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case SND_SOC_CLOCK_IN: |
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iismod |= S3C64XX_IISMOD_CDCLKCON; |
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break; |
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case SND_SOC_CLOCK_OUT: |
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iismod &= ~S3C64XX_IISMOD_CDCLKCON; |
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break; |
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default: |
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return -EINVAL; |
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} |
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break; |
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default: |
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return -EINVAL; |
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} |
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writel(iismod, i2s->regs + S3C2412_IISMOD); |
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pr_debug("%s w: IISMOD: %x\n", __func__, iismod); |
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return 0; |
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} |
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static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
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struct s3c_i2sv2_info *i2s = to_info(asoc_rtd_to_cpu(rtd, 0)); |
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int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE); |
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unsigned long irqs; |
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int ret = 0; |
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pr_debug("Entered %s\n", __func__); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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/* On start, ensure that the FIFOs are cleared and reset. */ |
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writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH, |
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i2s->regs + S3C2412_IISFIC); |
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/* clear again, just in case */ |
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writel(0x0, i2s->regs + S3C2412_IISFIC); |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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if (!i2s->master) { |
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ret = s3c2412_snd_lrsync(i2s); |
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if (ret) |
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goto exit_err; |
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} |
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local_irq_save(irqs); |
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if (capture) |
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s3c2412_snd_rxctrl(i2s, 1); |
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else |
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s3c2412_snd_txctrl(i2s, 1); |
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local_irq_restore(irqs); |
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break; |
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case SNDRV_PCM_TRIGGER_STOP: |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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local_irq_save(irqs); |
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if (capture) |
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s3c2412_snd_rxctrl(i2s, 0); |
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else |
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s3c2412_snd_txctrl(i2s, 0); |
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local_irq_restore(irqs); |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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exit_err: |
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return ret; |
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} |
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/* |
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* Set S3C2412 Clock dividers |
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*/ |
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static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, |
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int div_id, int div) |
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{ |
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struct s3c_i2sv2_info *i2s = to_info(cpu_dai); |
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u32 reg; |
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pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div); |
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switch (div_id) { |
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case S3C_I2SV2_DIV_BCLK: |
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switch (div) { |
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case 16: |
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div = S3C2412_IISMOD_BCLK_16FS; |
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break; |
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case 32: |
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div = S3C2412_IISMOD_BCLK_32FS; |
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break; |
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case 24: |
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div = S3C2412_IISMOD_BCLK_24FS; |
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break; |
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case 48: |
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div = S3C2412_IISMOD_BCLK_48FS; |
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break; |
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default: |
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return -EINVAL; |
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} |
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reg = readl(i2s->regs + S3C2412_IISMOD); |
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reg &= ~S3C2412_IISMOD_BCLK_MASK; |
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writel(reg | div, i2s->regs + S3C2412_IISMOD); |
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pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD)); |
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break; |
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case S3C_I2SV2_DIV_RCLK: |
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switch (div) { |
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case 256: |
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div = S3C2412_IISMOD_RCLK_256FS; |
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break; |
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case 384: |
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div = S3C2412_IISMOD_RCLK_384FS; |
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break; |
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case 512: |
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div = S3C2412_IISMOD_RCLK_512FS; |
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break; |
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case 768: |
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div = S3C2412_IISMOD_RCLK_768FS; |
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break; |
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default: |
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return -EINVAL; |
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} |
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reg = readl(i2s->regs + S3C2412_IISMOD); |
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reg &= ~S3C2412_IISMOD_RCLK_MASK; |
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writel(reg | div, i2s->regs + S3C2412_IISMOD); |
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pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD)); |
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break; |
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case S3C_I2SV2_DIV_PRESCALER: |
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if (div >= 0) { |
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writel((div << 8) | S3C2412_IISPSR_PSREN, |
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i2s->regs + S3C2412_IISPSR); |
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} else { |
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writel(0x0, i2s->regs + S3C2412_IISPSR); |
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} |
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pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR)); |
|
break; |
|
|
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct s3c_i2sv2_info *i2s = to_info(dai); |
|
u32 reg = readl(i2s->regs + S3C2412_IISFIC); |
|
snd_pcm_sframes_t delay; |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
|
delay = S3C2412_IISFIC_TXCOUNT(reg); |
|
else |
|
delay = S3C2412_IISFIC_RXCOUNT(reg); |
|
|
|
return delay; |
|
} |
|
|
|
struct clk *s3c_i2sv2_get_clock(struct snd_soc_dai *cpu_dai) |
|
{ |
|
struct s3c_i2sv2_info *i2s = to_info(cpu_dai); |
|
u32 iismod = readl(i2s->regs + S3C2412_IISMOD); |
|
|
|
if (iismod & S3C2412_IISMOD_IMS_SYSMUX) |
|
return i2s->iis_cclk; |
|
else |
|
return i2s->iis_pclk; |
|
} |
|
EXPORT_SYMBOL_GPL(s3c_i2sv2_get_clock); |
|
|
|
/* default table of all avaialable root fs divisors */ |
|
static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 }; |
|
|
|
int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info, |
|
unsigned int *fstab, |
|
unsigned int rate, struct clk *clk) |
|
{ |
|
unsigned long clkrate = clk_get_rate(clk); |
|
unsigned int div; |
|
unsigned int fsclk; |
|
unsigned int actual; |
|
unsigned int fs; |
|
unsigned int fsdiv; |
|
signed int deviation = 0; |
|
unsigned int best_fs = 0; |
|
unsigned int best_div = 0; |
|
unsigned int best_rate = 0; |
|
unsigned int best_deviation = INT_MAX; |
|
|
|
pr_debug("Input clock rate %ldHz\n", clkrate); |
|
|
|
if (fstab == NULL) |
|
fstab = iis_fs_tab; |
|
|
|
for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) { |
|
fsdiv = iis_fs_tab[fs]; |
|
|
|
fsclk = clkrate / fsdiv; |
|
div = fsclk / rate; |
|
|
|
if ((fsclk % rate) > (rate / 2)) |
|
div++; |
|
|
|
if (div <= 1) |
|
continue; |
|
|
|
actual = clkrate / (fsdiv * div); |
|
deviation = actual - rate; |
|
|
|
printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n", |
|
fsdiv, div, actual, deviation); |
|
|
|
deviation = abs(deviation); |
|
|
|
if (deviation < best_deviation) { |
|
best_fs = fsdiv; |
|
best_div = div; |
|
best_rate = actual; |
|
best_deviation = deviation; |
|
} |
|
|
|
if (deviation == 0) |
|
break; |
|
} |
|
|
|
printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n", |
|
best_fs, best_div, best_rate); |
|
|
|
info->fs_div = best_fs; |
|
info->clk_div = best_div; |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate); |
|
|
|
int s3c_i2sv2_probe(struct snd_soc_dai *dai, |
|
struct s3c_i2sv2_info *i2s) |
|
{ |
|
struct device *dev = dai->dev; |
|
unsigned int iismod; |
|
|
|
i2s->dev = dev; |
|
|
|
/* record our i2s structure for later use in the callbacks */ |
|
snd_soc_dai_set_drvdata(dai, i2s); |
|
|
|
i2s->iis_pclk = clk_get(dev, "iis"); |
|
if (IS_ERR(i2s->iis_pclk)) { |
|
dev_err(dev, "failed to get iis_clock\n"); |
|
return -ENOENT; |
|
} |
|
|
|
clk_prepare_enable(i2s->iis_pclk); |
|
|
|
/* Mark ourselves as in TXRX mode so we can run through our cleanup |
|
* process without warnings. */ |
|
iismod = readl(i2s->regs + S3C2412_IISMOD); |
|
iismod |= S3C2412_IISMOD_MODE_TXRX; |
|
writel(iismod, i2s->regs + S3C2412_IISMOD); |
|
s3c2412_snd_txctrl(i2s, 0); |
|
s3c2412_snd_rxctrl(i2s, 0); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(s3c_i2sv2_probe); |
|
|
|
void s3c_i2sv2_cleanup(struct snd_soc_dai *dai, |
|
struct s3c_i2sv2_info *i2s) |
|
{ |
|
clk_disable_unprepare(i2s->iis_pclk); |
|
clk_put(i2s->iis_pclk); |
|
i2s->iis_pclk = NULL; |
|
} |
|
EXPORT_SYMBOL_GPL(s3c_i2sv2_cleanup); |
|
|
|
int s3c_i2sv2_register_component(struct device *dev, int id, |
|
const struct snd_soc_component_driver *cmp_drv, |
|
struct snd_soc_dai_driver *dai_drv) |
|
{ |
|
struct snd_soc_dai_ops *ops = (struct snd_soc_dai_ops *)dai_drv->ops; |
|
|
|
ops->trigger = s3c2412_i2s_trigger; |
|
if (!ops->hw_params) |
|
ops->hw_params = s3c_i2sv2_hw_params; |
|
ops->set_fmt = s3c2412_i2s_set_fmt; |
|
ops->set_clkdiv = s3c2412_i2s_set_clkdiv; |
|
ops->set_sysclk = s3c_i2sv2_set_sysclk; |
|
|
|
/* Allow overriding by (for example) IISv4 */ |
|
if (!ops->delay) |
|
ops->delay = s3c2412_i2s_delay; |
|
|
|
return devm_snd_soc_register_component(dev, cmp_drv, dai_drv, 1); |
|
} |
|
EXPORT_SYMBOL_GPL(s3c_i2sv2_register_component); |
|
|
|
MODULE_LICENSE("GPL");
|
|
|