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162 lines
4.3 KiB
162 lines
4.3 KiB
/* |
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* Copyright (c) 2010 Google, Inc |
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* Copyright (c) 2014 NVIDIA Corporation |
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* |
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* Author: |
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* Colin Cross <[email protected]> |
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* |
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* This software is licensed under the terms of the GNU General Public |
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* License version 2, as published by the Free Software Foundation, and |
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* may be copied, distributed, and modified under those terms. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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*/ |
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#ifndef __SOC_TEGRA_PMC_H__ |
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#define __SOC_TEGRA_PMC_H__ |
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#include <linux/reboot.h> |
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#include <soc/tegra/pm.h> |
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struct clk; |
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struct reset_control; |
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#ifdef CONFIG_PM_SLEEP |
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enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); |
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void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode); |
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void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode); |
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#endif /* CONFIG_PM_SLEEP */ |
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#ifdef CONFIG_SMP |
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bool tegra_pmc_cpu_is_powered(unsigned int cpuid); |
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int tegra_pmc_cpu_power_on(unsigned int cpuid); |
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int tegra_pmc_cpu_remove_clamping(unsigned int cpuid); |
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#endif /* CONFIG_SMP */ |
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/* |
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* powergate and I/O rail APIs |
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*/ |
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#define TEGRA_POWERGATE_CPU 0 |
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#define TEGRA_POWERGATE_3D 1 |
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#define TEGRA_POWERGATE_VENC 2 |
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#define TEGRA_POWERGATE_PCIE 3 |
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#define TEGRA_POWERGATE_VDEC 4 |
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#define TEGRA_POWERGATE_L2 5 |
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#define TEGRA_POWERGATE_MPE 6 |
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#define TEGRA_POWERGATE_HEG 7 |
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#define TEGRA_POWERGATE_SATA 8 |
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#define TEGRA_POWERGATE_CPU1 9 |
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#define TEGRA_POWERGATE_CPU2 10 |
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#define TEGRA_POWERGATE_CPU3 11 |
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#define TEGRA_POWERGATE_CELP 12 |
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#define TEGRA_POWERGATE_3D1 13 |
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#define TEGRA_POWERGATE_CPU0 14 |
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#define TEGRA_POWERGATE_C0NC 15 |
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#define TEGRA_POWERGATE_C1NC 16 |
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#define TEGRA_POWERGATE_SOR 17 |
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#define TEGRA_POWERGATE_DIS 18 |
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#define TEGRA_POWERGATE_DISB 19 |
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#define TEGRA_POWERGATE_XUSBA 20 |
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#define TEGRA_POWERGATE_XUSBB 21 |
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#define TEGRA_POWERGATE_XUSBC 22 |
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#define TEGRA_POWERGATE_VIC 23 |
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#define TEGRA_POWERGATE_IRAM 24 |
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#define TEGRA_POWERGATE_NVDEC 25 |
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#define TEGRA_POWERGATE_NVJPG 26 |
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#define TEGRA_POWERGATE_AUD 27 |
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#define TEGRA_POWERGATE_DFD 28 |
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#define TEGRA_POWERGATE_VE2 29 |
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#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2 |
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#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D |
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#define TEGRA_IO_RAIL_CSIA 0 |
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#define TEGRA_IO_RAIL_CSIB 1 |
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#define TEGRA_IO_RAIL_DSI 2 |
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#define TEGRA_IO_RAIL_MIPI_BIAS 3 |
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#define TEGRA_IO_RAIL_PEX_BIAS 4 |
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#define TEGRA_IO_RAIL_PEX_CLK1 5 |
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#define TEGRA_IO_RAIL_PEX_CLK2 6 |
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#define TEGRA_IO_RAIL_USB0 9 |
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#define TEGRA_IO_RAIL_USB1 10 |
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#define TEGRA_IO_RAIL_USB2 11 |
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#define TEGRA_IO_RAIL_USB_BIAS 12 |
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#define TEGRA_IO_RAIL_NAND 13 |
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#define TEGRA_IO_RAIL_UART 14 |
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#define TEGRA_IO_RAIL_BB 15 |
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#define TEGRA_IO_RAIL_AUDIO 17 |
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#define TEGRA_IO_RAIL_HSIC 19 |
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#define TEGRA_IO_RAIL_COMP 22 |
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#define TEGRA_IO_RAIL_HDMI 28 |
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#define TEGRA_IO_RAIL_PEX_CNTRL 32 |
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#define TEGRA_IO_RAIL_SDMMC1 33 |
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#define TEGRA_IO_RAIL_SDMMC3 34 |
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#define TEGRA_IO_RAIL_SDMMC4 35 |
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#define TEGRA_IO_RAIL_CAM 36 |
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#define TEGRA_IO_RAIL_RES 37 |
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#define TEGRA_IO_RAIL_HV 38 |
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#define TEGRA_IO_RAIL_DSIB 39 |
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#define TEGRA_IO_RAIL_DSIC 40 |
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#define TEGRA_IO_RAIL_DSID 41 |
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#define TEGRA_IO_RAIL_CSIE 44 |
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#define TEGRA_IO_RAIL_LVDS 57 |
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#define TEGRA_IO_RAIL_SYS_DDC 58 |
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#ifdef CONFIG_ARCH_TEGRA |
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int tegra_powergate_is_powered(unsigned int id); |
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int tegra_powergate_power_on(unsigned int id); |
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int tegra_powergate_power_off(unsigned int id); |
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int tegra_powergate_remove_clamping(unsigned int id); |
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/* Must be called with clk disabled, and returns with clk enabled */ |
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int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, |
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struct reset_control *rst); |
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int tegra_io_rail_power_on(unsigned int id); |
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int tegra_io_rail_power_off(unsigned int id); |
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#else |
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static inline int tegra_powergate_is_powered(unsigned int id) |
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{ |
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return -ENOSYS; |
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} |
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static inline int tegra_powergate_power_on(unsigned int id) |
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{ |
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return -ENOSYS; |
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} |
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static inline int tegra_powergate_power_off(unsigned int id) |
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{ |
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return -ENOSYS; |
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} |
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static inline int tegra_powergate_remove_clamping(unsigned int id) |
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{ |
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return -ENOSYS; |
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} |
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static inline int tegra_powergate_sequence_power_up(unsigned int id, |
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struct clk *clk, |
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struct reset_control *rst) |
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{ |
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return -ENOSYS; |
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} |
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static inline int tegra_io_rail_power_on(unsigned int id) |
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{ |
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return -ENOSYS; |
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} |
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static inline int tegra_io_rail_power_off(unsigned int id) |
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{ |
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return -ENOSYS; |
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} |
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#endif /* CONFIG_ARCH_TEGRA */ |
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#endif /* __SOC_TEGRA_PMC_H__ */
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