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299 lines
9.1 KiB
299 lines
9.1 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (c) 2006-2009 Simtec Electronics |
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* http://armlinux.simtec.co.uk/ |
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* Ben Dooks <[email protected]> |
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* |
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* S3C CPU frequency scaling support - core support |
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*/ |
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#ifndef __LINUX_SOC_SAMSUNG_S3C_CPUFREQ_CORE_H |
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#define __LINUX_SOC_SAMSUNG_S3C_CPUFREQ_CORE_H |
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#include <linux/soc/samsung/s3c-cpu-freq.h> |
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struct seq_file; |
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#define MAX_BANKS (8) |
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#define S3C2412_MAX_IO (8) |
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/** |
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* struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings |
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* @bankcon: The cached version of settings in this structure. |
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* @tacp: |
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* @tacs: Time from address valid to nCS asserted. |
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* @tcos: Time from nCS asserted to nOE or nWE asserted. |
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* @tacc: Time that nOE or nWE is asserted. |
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* @tcoh: Time nCS is held after nOE or nWE are released. |
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* @tcah: Time address is held for after |
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* @nwait_en: Whether nWAIT is enabled for this bank. |
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* |
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* This structure represents the IO timings for a S3C2410 style IO bank |
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* used by the CPU frequency support if it needs to change the settings |
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* of the IO. |
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*/ |
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struct s3c2410_iobank_timing { |
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unsigned long bankcon; |
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unsigned int tacp; |
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unsigned int tacs; |
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unsigned int tcos; |
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unsigned int tacc; |
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unsigned int tcoh; /* nCS hold after nOE/nWE */ |
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unsigned int tcah; /* Address hold after nCS */ |
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unsigned char nwait_en; /* nWait enabled for bank. */ |
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}; |
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/** |
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* struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO |
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* @idcy: The idle cycle time between transactions. |
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* @wstrd: nCS release to end of read cycle. |
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* @wstwr: nCS release to end of write cycle. |
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* @wstoen: nCS assertion to nOE assertion time. |
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* @wstwen: nCS assertion to nWE assertion time. |
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* @wstbrd: Burst ready delay. |
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* @smbidcyr: Register cache for smbidcyr value. |
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* @smbwstrd: Register cache for smbwstrd value. |
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* @smbwstwr: Register cache for smbwstwr value. |
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* @smbwstoen: Register cache for smbwstoen value. |
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* @smbwstwen: Register cache for smbwstwen value. |
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* @smbwstbrd: Register cache for smbwstbrd value. |
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* |
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* Timing information for a IO bank on an S3C2412 or similar system which |
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* uses a PL093 block. |
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*/ |
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struct s3c2412_iobank_timing { |
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unsigned int idcy; |
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unsigned int wstrd; |
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unsigned int wstwr; |
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unsigned int wstoen; |
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unsigned int wstwen; |
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unsigned int wstbrd; |
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/* register cache */ |
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unsigned char smbidcyr; |
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unsigned char smbwstrd; |
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unsigned char smbwstwr; |
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unsigned char smbwstoen; |
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unsigned char smbwstwen; |
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unsigned char smbwstbrd; |
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}; |
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union s3c_iobank { |
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struct s3c2410_iobank_timing *io_2410; |
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struct s3c2412_iobank_timing *io_2412; |
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}; |
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/** |
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* struct s3c_iotimings - Chip IO timings holder |
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* @bank: The timings for each IO bank. |
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*/ |
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struct s3c_iotimings { |
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union s3c_iobank bank[MAX_BANKS]; |
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}; |
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/** |
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* struct s3c_plltab - PLL table information. |
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* @vals: List of PLL values. |
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* @size: Size of the PLL table @vals. |
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*/ |
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struct s3c_plltab { |
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struct s3c_pllval *vals; |
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int size; |
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}; |
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/** |
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* struct s3c_cpufreq_config - current cpu frequency configuration |
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* @freq: The current settings for the core clocks. |
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* @max: Maxium settings, derived from core, board and user settings. |
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* @pll: The PLL table entry for the current PLL settings. |
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* @divs: The divisor settings for the core clocks. |
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* @info: The current core driver information. |
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* @board: The information for the board we are running on. |
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* @lock_pll: Set if the PLL settings cannot be changed. |
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* |
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* This is for the core drivers that need to know information about |
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* the current settings and values. It should not be needed by any |
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* device drivers. |
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*/ |
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struct s3c_cpufreq_config { |
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struct s3c_freq freq; |
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struct s3c_freq max; |
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struct clk *mpll; |
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struct cpufreq_frequency_table pll; |
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struct s3c_clkdivs divs; |
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struct s3c_cpufreq_info *info; /* for core, not drivers */ |
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struct s3c_cpufreq_board *board; |
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unsigned int lock_pll:1; |
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}; |
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/** |
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* struct s3c_cpufreq_info - Information for the CPU frequency driver. |
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* @name: The name of this implementation. |
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* @max: The maximum frequencies for the system. |
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* @latency: Transition latency to give to cpufreq. |
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* @locktime_m: The lock-time in uS for the MPLL. |
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* @locktime_u: The lock-time in uS for the UPLL. |
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* @locttime_bits: The number of bits each LOCKTIME field. |
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* @need_pll: Set if this driver needs to change the PLL values to achieve |
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* any frequency changes. This is really only need by devices like the |
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* S3C2410 where there is no or limited divider between the PLL and the |
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* ARMCLK. |
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* @get_iotiming: Get the current IO timing data, mainly for use at start. |
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* @set_iotiming: Update the IO timings from the cached copies calculated |
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* from the @calc_iotiming entry when changing the frequency. |
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* @calc_iotiming: Calculate and update the cached copies of the IO timings |
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* from the newly calculated frequencies. |
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* @calc_freqtable: Calculate (fill in) the given frequency table from the |
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* current frequency configuration. If the table passed in is NULL, |
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* then the return is the number of elements to be filled for allocation |
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* of the table. |
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* @set_refresh: Set the memory refresh configuration. |
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* @set_fvco: Set the PLL frequencies. |
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* @set_divs: Update the clock divisors. |
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* @calc_divs: Calculate the clock divisors. |
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*/ |
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struct s3c_cpufreq_info { |
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const char *name; |
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struct s3c_freq max; |
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unsigned int latency; |
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unsigned int locktime_m; |
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unsigned int locktime_u; |
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unsigned char locktime_bits; |
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unsigned int need_pll:1; |
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/* driver routines */ |
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int (*get_iotiming)(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *timings); |
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void (*set_iotiming)(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *timings); |
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int (*calc_iotiming)(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *timings); |
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int (*calc_freqtable)(struct s3c_cpufreq_config *cfg, |
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struct cpufreq_frequency_table *t, |
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size_t table_size); |
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void (*debug_io_show)(struct seq_file *seq, |
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struct s3c_cpufreq_config *cfg, |
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union s3c_iobank *iob); |
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void (*set_refresh)(struct s3c_cpufreq_config *cfg); |
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void (*set_fvco)(struct s3c_cpufreq_config *cfg); |
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void (*set_divs)(struct s3c_cpufreq_config *cfg); |
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int (*calc_divs)(struct s3c_cpufreq_config *cfg); |
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}; |
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extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); |
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extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, |
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unsigned int plls_no); |
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/* exports and utilities for debugfs */ |
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extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); |
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extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); |
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS |
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#define s3c_cpufreq_debugfs_call(x) x |
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#else |
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#define s3c_cpufreq_debugfs_call(x) NULL |
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#endif |
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/* Useful utility functions. */ |
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extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *); |
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/* S3C2410 and compatible exported functions */ |
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extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); |
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extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg); |
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#ifdef CONFIG_S3C2410_IOTIMING |
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extern void s3c2410_iotiming_debugfs(struct seq_file *seq, |
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struct s3c_cpufreq_config *cfg, |
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union s3c_iobank *iob); |
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extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *iot); |
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extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *timings); |
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extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *iot); |
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#else |
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#define s3c2410_iotiming_debugfs NULL |
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#define s3c2410_iotiming_calc NULL |
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#define s3c2410_iotiming_get NULL |
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#define s3c2410_iotiming_set NULL |
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#endif /* CONFIG_S3C2410_IOTIMING */ |
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/* S3C2412 compatible routines */ |
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#ifdef CONFIG_S3C2412_IOTIMING |
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extern void s3c2412_iotiming_debugfs(struct seq_file *seq, |
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struct s3c_cpufreq_config *cfg, |
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union s3c_iobank *iob); |
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extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *timings); |
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extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *iot); |
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extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, |
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struct s3c_iotimings *iot); |
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extern void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); |
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#else |
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#define s3c2412_iotiming_debugfs NULL |
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#define s3c2412_iotiming_calc NULL |
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#define s3c2412_iotiming_get NULL |
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#define s3c2412_iotiming_set NULL |
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#endif /* CONFIG_S3C2412_IOTIMING */ |
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG |
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#define s3c_freq_dbg(x...) printk(KERN_INFO x) |
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#else |
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#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) |
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#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */ |
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG |
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#define s3c_freq_iodbg(x...) printk(KERN_INFO x) |
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#else |
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#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) |
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#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */ |
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static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, |
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int index, size_t table_size, |
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unsigned int freq) |
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{ |
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if (index < 0) |
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return index; |
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if (table) { |
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if (index >= table_size) |
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return -ENOMEM; |
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s3c_freq_dbg("%s: { %d = %u kHz }\n", |
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__func__, index, freq); |
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table[index].driver_data = index; |
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table[index].frequency = freq; |
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} |
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return index + 1; |
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} |
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u32 s3c2440_read_camdivn(void); |
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void s3c2440_write_camdivn(u32 camdiv); |
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u32 s3c24xx_read_clkdivn(void); |
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void s3c24xx_write_clkdivn(u32 clkdiv); |
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u32 s3c24xx_read_mpllcon(void); |
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void s3c24xx_write_locktime(u32 locktime); |
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#endif
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