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691 lines
18 KiB
691 lines
18 KiB
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
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/* QLogic qed NIC Driver |
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* Copyright (c) 2015-2017 QLogic Corporation |
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* Copyright (c) 2019-2020 Marvell International Ltd. |
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*/ |
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#ifndef _QED_RDMA_IF_H |
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#define _QED_RDMA_IF_H |
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#include <linux/types.h> |
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#include <linux/delay.h> |
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#include <linux/list.h> |
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#include <linux/slab.h> |
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#include <linux/qed/qed_if.h> |
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#include <linux/qed/qed_ll2_if.h> |
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#include <linux/qed/rdma_common.h> |
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#define QED_RDMA_MAX_CNQ_SIZE (0xFFFF) |
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/* rdma interface */ |
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enum qed_roce_qp_state { |
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QED_ROCE_QP_STATE_RESET, |
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QED_ROCE_QP_STATE_INIT, |
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QED_ROCE_QP_STATE_RTR, |
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QED_ROCE_QP_STATE_RTS, |
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QED_ROCE_QP_STATE_SQD, |
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QED_ROCE_QP_STATE_ERR, |
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QED_ROCE_QP_STATE_SQE |
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}; |
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enum qed_rdma_qp_type { |
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QED_RDMA_QP_TYPE_RC, |
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QED_RDMA_QP_TYPE_XRC_INI, |
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QED_RDMA_QP_TYPE_XRC_TGT, |
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QED_RDMA_QP_TYPE_INVAL = 0xffff, |
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}; |
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enum qed_rdma_tid_type { |
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QED_RDMA_TID_REGISTERED_MR, |
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QED_RDMA_TID_FMR, |
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QED_RDMA_TID_MW |
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}; |
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struct qed_rdma_events { |
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void *context; |
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void (*affiliated_event)(void *context, u8 fw_event_code, |
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void *fw_handle); |
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void (*unaffiliated_event)(void *context, u8 event_code); |
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}; |
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struct qed_rdma_device { |
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u32 vendor_id; |
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u32 vendor_part_id; |
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u32 hw_ver; |
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u64 fw_ver; |
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u64 node_guid; |
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u64 sys_image_guid; |
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u8 max_cnq; |
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u8 max_sge; |
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u8 max_srq_sge; |
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u16 max_inline; |
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u32 max_wqe; |
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u32 max_srq_wqe; |
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u8 max_qp_resp_rd_atomic_resc; |
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u8 max_qp_req_rd_atomic_resc; |
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u64 max_dev_resp_rd_atomic_resc; |
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u32 max_cq; |
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u32 max_qp; |
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u32 max_srq; |
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u32 max_mr; |
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u64 max_mr_size; |
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u32 max_cqe; |
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u32 max_mw; |
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u32 max_mr_mw_fmr_pbl; |
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u64 max_mr_mw_fmr_size; |
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u32 max_pd; |
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u32 max_ah; |
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u8 max_pkey; |
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u16 max_srq_wr; |
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u8 max_stats_queues; |
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u32 dev_caps; |
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/* Abilty to support RNR-NAK generation */ |
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#define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT 0 |
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/* Abilty to support shutdown port */ |
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#define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1 |
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/* Abilty to support port active event */ |
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#define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2 |
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/* Abilty to support port change event */ |
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#define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3 |
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/* Abilty to support system image GUID */ |
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#define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4 |
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/* Abilty to support bad P_Key counter support */ |
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#define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5 |
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/* Abilty to support atomic operations */ |
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#define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6 |
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#define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7 |
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/* Abilty to support modifying the maximum number of |
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* outstanding work requests per QP |
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*/ |
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#define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8 |
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/* Abilty to support automatic path migration */ |
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#define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9 |
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/* Abilty to support the base memory management extensions */ |
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#define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10 |
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#define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11 |
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/* Abilty to support multipile page sizes per memory region */ |
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#define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12 |
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/* Abilty to support block list physical buffer list */ |
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#define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13 |
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/* Abilty to support zero based virtual addresses */ |
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#define QED_RDMA_DEV_CAP_ZBVA_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_ZBVA_SHIFT 14 |
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/* Abilty to support local invalidate fencing */ |
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#define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15 |
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/* Abilty to support Loopback on QP */ |
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#define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1 |
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#define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16 |
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u64 page_size_caps; |
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u8 dev_ack_delay; |
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u32 reserved_lkey; |
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u32 bad_pkey_counter; |
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struct qed_rdma_events events; |
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}; |
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enum qed_port_state { |
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QED_RDMA_PORT_UP, |
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QED_RDMA_PORT_DOWN, |
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}; |
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enum qed_roce_capability { |
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QED_ROCE_V1 = 1 << 0, |
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QED_ROCE_V2 = 1 << 1, |
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}; |
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struct qed_rdma_port { |
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enum qed_port_state port_state; |
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int link_speed; |
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u64 max_msg_size; |
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u8 source_gid_table_len; |
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void *source_gid_table_ptr; |
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u8 pkey_table_len; |
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void *pkey_table_ptr; |
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u32 pkey_bad_counter; |
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enum qed_roce_capability capability; |
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}; |
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struct qed_rdma_cnq_params { |
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u8 num_pbl_pages; |
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u64 pbl_ptr; |
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}; |
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/* The CQ Mode affects the CQ doorbell transaction size. |
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* 64/32 bit machines should configure to 32/16 bits respectively. |
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*/ |
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enum qed_rdma_cq_mode { |
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QED_RDMA_CQ_MODE_16_BITS, |
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QED_RDMA_CQ_MODE_32_BITS, |
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}; |
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struct qed_roce_dcqcn_params { |
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u8 notification_point; |
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u8 reaction_point; |
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/* fields for notification point */ |
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u32 cnp_send_timeout; |
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/* fields for reaction point */ |
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u32 rl_bc_rate; |
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u16 rl_max_rate; |
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u16 rl_r_ai; |
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u16 rl_r_hai; |
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u16 dcqcn_g; |
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u32 dcqcn_k_us; |
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u32 dcqcn_timeout_us; |
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}; |
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struct qed_rdma_start_in_params { |
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struct qed_rdma_events *events; |
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struct qed_rdma_cnq_params cnq_pbl_list[128]; |
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u8 desired_cnq; |
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enum qed_rdma_cq_mode cq_mode; |
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struct qed_roce_dcqcn_params dcqcn_params; |
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u16 max_mtu; |
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u8 mac_addr[ETH_ALEN]; |
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u8 iwarp_flags; |
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}; |
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struct qed_rdma_add_user_out_params { |
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u16 dpi; |
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void __iomem *dpi_addr; |
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u64 dpi_phys_addr; |
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u32 dpi_size; |
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u16 wid_count; |
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}; |
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enum roce_mode { |
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ROCE_V1, |
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ROCE_V2_IPV4, |
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ROCE_V2_IPV6, |
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MAX_ROCE_MODE |
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}; |
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union qed_gid { |
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u8 bytes[16]; |
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u16 words[8]; |
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u32 dwords[4]; |
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u64 qwords[2]; |
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u32 ipv4_addr; |
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}; |
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struct qed_rdma_register_tid_in_params { |
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u32 itid; |
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enum qed_rdma_tid_type tid_type; |
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u8 key; |
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u16 pd; |
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bool local_read; |
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bool local_write; |
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bool remote_read; |
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bool remote_write; |
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bool remote_atomic; |
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bool mw_bind; |
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u64 pbl_ptr; |
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bool pbl_two_level; |
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u8 pbl_page_size_log; |
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u8 page_size_log; |
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u64 length; |
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u64 vaddr; |
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bool phy_mr; |
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bool dma_mr; |
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bool dif_enabled; |
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u64 dif_error_addr; |
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}; |
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struct qed_rdma_create_cq_in_params { |
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u32 cq_handle_lo; |
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u32 cq_handle_hi; |
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u32 cq_size; |
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u16 dpi; |
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bool pbl_two_level; |
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u64 pbl_ptr; |
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u16 pbl_num_pages; |
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u8 pbl_page_size_log; |
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u8 cnq_id; |
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u16 int_timeout; |
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}; |
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struct qed_rdma_create_srq_in_params { |
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u64 pbl_base_addr; |
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u64 prod_pair_addr; |
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u16 num_pages; |
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u16 pd_id; |
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u16 page_size; |
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/* XRC related only */ |
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bool reserved_key_en; |
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bool is_xrc; |
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u32 cq_cid; |
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u16 xrcd_id; |
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}; |
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struct qed_rdma_destroy_cq_in_params { |
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u16 icid; |
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}; |
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struct qed_rdma_destroy_cq_out_params { |
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u16 num_cq_notif; |
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}; |
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struct qed_rdma_create_qp_in_params { |
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u32 qp_handle_lo; |
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u32 qp_handle_hi; |
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u32 qp_handle_async_lo; |
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u32 qp_handle_async_hi; |
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bool use_srq; |
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bool signal_all; |
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bool fmr_and_reserved_lkey; |
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u16 pd; |
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u16 dpi; |
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u16 sq_cq_id; |
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u16 sq_num_pages; |
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u64 sq_pbl_ptr; |
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u8 max_sq_sges; |
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u16 rq_cq_id; |
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u16 rq_num_pages; |
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u64 rq_pbl_ptr; |
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u16 srq_id; |
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u16 xrcd_id; |
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u8 stats_queue; |
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enum qed_rdma_qp_type qp_type; |
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u8 flags; |
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#define QED_ROCE_EDPM_MODE_MASK 0x1 |
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#define QED_ROCE_EDPM_MODE_SHIFT 0 |
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}; |
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struct qed_rdma_create_qp_out_params { |
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u32 qp_id; |
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u16 icid; |
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void *rq_pbl_virt; |
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dma_addr_t rq_pbl_phys; |
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void *sq_pbl_virt; |
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dma_addr_t sq_pbl_phys; |
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}; |
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struct qed_rdma_modify_qp_in_params { |
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u32 modify_flags; |
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#define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1 |
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#define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0 |
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#define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1 |
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#define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1 |
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#define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2 |
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#define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3 |
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#define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4 |
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#define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5 |
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#define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6 |
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#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1 |
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#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7 |
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#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1 |
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#define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8 |
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#define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9 |
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#define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10 |
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#define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11 |
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#define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12 |
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#define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13 |
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#define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1 |
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#define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14 |
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enum qed_roce_qp_state new_state; |
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u16 pkey; |
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bool incoming_rdma_read_en; |
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bool incoming_rdma_write_en; |
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bool incoming_atomic_en; |
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bool e2e_flow_control_en; |
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u32 dest_qp; |
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bool lb_indication; |
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u16 mtu; |
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u8 traffic_class_tos; |
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u8 hop_limit_ttl; |
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u32 flow_label; |
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union qed_gid sgid; |
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union qed_gid dgid; |
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u16 udp_src_port; |
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u16 vlan_id; |
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u32 rq_psn; |
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u32 sq_psn; |
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u8 max_rd_atomic_resp; |
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u8 max_rd_atomic_req; |
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u32 ack_timeout; |
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u8 retry_cnt; |
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u8 rnr_retry_cnt; |
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u8 min_rnr_nak_timer; |
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bool sqd_async; |
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u8 remote_mac_addr[6]; |
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u8 local_mac_addr[6]; |
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bool use_local_mac; |
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enum roce_mode roce_mode; |
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}; |
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struct qed_rdma_query_qp_out_params { |
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enum qed_roce_qp_state state; |
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u32 rq_psn; |
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u32 sq_psn; |
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bool draining; |
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u16 mtu; |
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u32 dest_qp; |
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bool incoming_rdma_read_en; |
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bool incoming_rdma_write_en; |
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bool incoming_atomic_en; |
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bool e2e_flow_control_en; |
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union qed_gid sgid; |
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union qed_gid dgid; |
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u32 flow_label; |
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u8 hop_limit_ttl; |
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u8 traffic_class_tos; |
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u32 timeout; |
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u8 rnr_retry; |
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u8 retry_cnt; |
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u8 min_rnr_nak_timer; |
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u16 pkey_index; |
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u8 max_rd_atomic; |
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u8 max_dest_rd_atomic; |
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bool sqd_async; |
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}; |
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struct qed_rdma_create_srq_out_params { |
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u16 srq_id; |
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}; |
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struct qed_rdma_destroy_srq_in_params { |
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u16 srq_id; |
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bool is_xrc; |
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}; |
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struct qed_rdma_modify_srq_in_params { |
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u32 wqe_limit; |
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u16 srq_id; |
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bool is_xrc; |
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}; |
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struct qed_rdma_stats_out_params { |
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u64 sent_bytes; |
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u64 sent_pkts; |
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u64 rcv_bytes; |
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u64 rcv_pkts; |
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}; |
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struct qed_rdma_counters_out_params { |
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u64 pd_count; |
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u64 max_pd; |
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u64 dpi_count; |
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u64 max_dpi; |
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u64 cq_count; |
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u64 max_cq; |
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u64 qp_count; |
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u64 max_qp; |
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u64 tid_count; |
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u64 max_tid; |
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}; |
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#define QED_ROCE_TX_HEAD_FAILURE (1) |
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#define QED_ROCE_TX_FRAG_FAILURE (2) |
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enum qed_iwarp_event_type { |
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QED_IWARP_EVENT_MPA_REQUEST, /* Passive side request received */ |
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QED_IWARP_EVENT_PASSIVE_COMPLETE, /* ack on mpa response */ |
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QED_IWARP_EVENT_ACTIVE_COMPLETE, /* Active side reply received */ |
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QED_IWARP_EVENT_DISCONNECT, |
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QED_IWARP_EVENT_CLOSE, |
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QED_IWARP_EVENT_IRQ_FULL, |
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QED_IWARP_EVENT_RQ_EMPTY, |
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QED_IWARP_EVENT_LLP_TIMEOUT, |
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QED_IWARP_EVENT_REMOTE_PROTECTION_ERROR, |
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QED_IWARP_EVENT_CQ_OVERFLOW, |
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QED_IWARP_EVENT_QP_CATASTROPHIC, |
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QED_IWARP_EVENT_ACTIVE_MPA_REPLY, |
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QED_IWARP_EVENT_LOCAL_ACCESS_ERROR, |
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QED_IWARP_EVENT_REMOTE_OPERATION_ERROR, |
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QED_IWARP_EVENT_TERMINATE_RECEIVED, |
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QED_IWARP_EVENT_SRQ_LIMIT, |
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QED_IWARP_EVENT_SRQ_EMPTY, |
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}; |
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enum qed_tcp_ip_version { |
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QED_TCP_IPV4, |
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QED_TCP_IPV6, |
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}; |
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struct qed_iwarp_cm_info { |
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enum qed_tcp_ip_version ip_version; |
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u32 remote_ip[4]; |
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u32 local_ip[4]; |
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u16 remote_port; |
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u16 local_port; |
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u16 vlan; |
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u8 ord; |
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u8 ird; |
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u16 private_data_len; |
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const void *private_data; |
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}; |
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struct qed_iwarp_cm_event_params { |
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enum qed_iwarp_event_type event; |
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const struct qed_iwarp_cm_info *cm_info; |
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void *ep_context; /* To be passed to accept call */ |
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int status; |
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}; |
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typedef int (*iwarp_event_handler) (void *context, |
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struct qed_iwarp_cm_event_params *event); |
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struct qed_iwarp_connect_in { |
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iwarp_event_handler event_cb; |
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void *cb_context; |
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struct qed_rdma_qp *qp; |
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struct qed_iwarp_cm_info cm_info; |
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u16 mss; |
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u8 remote_mac_addr[ETH_ALEN]; |
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u8 local_mac_addr[ETH_ALEN]; |
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}; |
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struct qed_iwarp_connect_out { |
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void *ep_context; |
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}; |
|
|
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struct qed_iwarp_listen_in { |
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iwarp_event_handler event_cb; |
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void *cb_context; /* passed to event_cb */ |
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u32 max_backlog; |
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enum qed_tcp_ip_version ip_version; |
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u32 ip_addr[4]; |
|
u16 port; |
|
u16 vlan; |
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}; |
|
|
|
struct qed_iwarp_listen_out { |
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void *handle; |
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}; |
|
|
|
struct qed_iwarp_accept_in { |
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void *ep_context; |
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void *cb_context; |
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struct qed_rdma_qp *qp; |
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const void *private_data; |
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u16 private_data_len; |
|
u8 ord; |
|
u8 ird; |
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}; |
|
|
|
struct qed_iwarp_reject_in { |
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void *ep_context; |
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void *cb_context; |
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const void *private_data; |
|
u16 private_data_len; |
|
}; |
|
|
|
struct qed_iwarp_send_rtr_in { |
|
void *ep_context; |
|
}; |
|
|
|
struct qed_roce_ll2_header { |
|
void *vaddr; |
|
dma_addr_t baddr; |
|
size_t len; |
|
}; |
|
|
|
struct qed_roce_ll2_buffer { |
|
dma_addr_t baddr; |
|
size_t len; |
|
}; |
|
|
|
struct qed_roce_ll2_packet { |
|
struct qed_roce_ll2_header header; |
|
int n_seg; |
|
struct qed_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE]; |
|
int roce_mode; |
|
enum qed_ll2_tx_dest tx_dest; |
|
}; |
|
|
|
enum qed_rdma_type { |
|
QED_RDMA_TYPE_ROCE, |
|
QED_RDMA_TYPE_IWARP |
|
}; |
|
|
|
struct qed_dev_rdma_info { |
|
struct qed_dev_info common; |
|
enum qed_rdma_type rdma_type; |
|
u8 user_dpm_enabled; |
|
}; |
|
|
|
struct qed_rdma_ops { |
|
const struct qed_common_ops *common; |
|
|
|
int (*fill_dev_info)(struct qed_dev *cdev, |
|
struct qed_dev_rdma_info *info); |
|
void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev); |
|
|
|
int (*rdma_init)(struct qed_dev *dev, |
|
struct qed_rdma_start_in_params *iparams); |
|
|
|
int (*rdma_add_user)(void *rdma_cxt, |
|
struct qed_rdma_add_user_out_params *oparams); |
|
|
|
void (*rdma_remove_user)(void *rdma_cxt, u16 dpi); |
|
int (*rdma_stop)(void *rdma_cxt); |
|
struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt); |
|
struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt); |
|
int (*rdma_get_start_sb)(struct qed_dev *cdev); |
|
int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev); |
|
void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod); |
|
int (*rdma_get_rdma_int)(struct qed_dev *cdev, |
|
struct qed_int_info *info); |
|
int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt); |
|
int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd); |
|
void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd); |
|
int (*rdma_alloc_xrcd)(void *rdma_cxt, u16 *xrcd); |
|
void (*rdma_dealloc_xrcd)(void *rdma_cxt, u16 xrcd); |
|
int (*rdma_create_cq)(void *rdma_cxt, |
|
struct qed_rdma_create_cq_in_params *params, |
|
u16 *icid); |
|
int (*rdma_destroy_cq)(void *rdma_cxt, |
|
struct qed_rdma_destroy_cq_in_params *iparams, |
|
struct qed_rdma_destroy_cq_out_params *oparams); |
|
struct qed_rdma_qp * |
|
(*rdma_create_qp)(void *rdma_cxt, |
|
struct qed_rdma_create_qp_in_params *iparams, |
|
struct qed_rdma_create_qp_out_params *oparams); |
|
|
|
int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp, |
|
struct qed_rdma_modify_qp_in_params *iparams); |
|
|
|
int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp, |
|
struct qed_rdma_query_qp_out_params *oparams); |
|
int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp); |
|
|
|
int |
|
(*rdma_register_tid)(void *rdma_cxt, |
|
struct qed_rdma_register_tid_in_params *iparams); |
|
|
|
int (*rdma_deregister_tid)(void *rdma_cxt, u32 itid); |
|
int (*rdma_alloc_tid)(void *rdma_cxt, u32 *itid); |
|
void (*rdma_free_tid)(void *rdma_cxt, u32 itid); |
|
|
|
int (*rdma_create_srq)(void *rdma_cxt, |
|
struct qed_rdma_create_srq_in_params *iparams, |
|
struct qed_rdma_create_srq_out_params *oparams); |
|
int (*rdma_destroy_srq)(void *rdma_cxt, |
|
struct qed_rdma_destroy_srq_in_params *iparams); |
|
int (*rdma_modify_srq)(void *rdma_cxt, |
|
struct qed_rdma_modify_srq_in_params *iparams); |
|
|
|
int (*ll2_acquire_connection)(void *rdma_cxt, |
|
struct qed_ll2_acquire_data *data); |
|
|
|
int (*ll2_establish_connection)(void *rdma_cxt, u8 connection_handle); |
|
int (*ll2_terminate_connection)(void *rdma_cxt, u8 connection_handle); |
|
void (*ll2_release_connection)(void *rdma_cxt, u8 connection_handle); |
|
|
|
int (*ll2_prepare_tx_packet)(void *rdma_cxt, |
|
u8 connection_handle, |
|
struct qed_ll2_tx_pkt_info *pkt, |
|
bool notify_fw); |
|
|
|
int (*ll2_set_fragment_of_tx_packet)(void *rdma_cxt, |
|
u8 connection_handle, |
|
dma_addr_t addr, |
|
u16 nbytes); |
|
int (*ll2_post_rx_buffer)(void *rdma_cxt, u8 connection_handle, |
|
dma_addr_t addr, u16 buf_len, void *cookie, |
|
u8 notify_fw); |
|
int (*ll2_get_stats)(void *rdma_cxt, |
|
u8 connection_handle, |
|
struct qed_ll2_stats *p_stats); |
|
int (*ll2_set_mac_filter)(struct qed_dev *cdev, |
|
u8 *old_mac_address, u8 *new_mac_address); |
|
|
|
int (*iwarp_set_engine_affin)(struct qed_dev *cdev, bool b_reset); |
|
|
|
int (*iwarp_connect)(void *rdma_cxt, |
|
struct qed_iwarp_connect_in *iparams, |
|
struct qed_iwarp_connect_out *oparams); |
|
|
|
int (*iwarp_create_listen)(void *rdma_cxt, |
|
struct qed_iwarp_listen_in *iparams, |
|
struct qed_iwarp_listen_out *oparams); |
|
|
|
int (*iwarp_accept)(void *rdma_cxt, |
|
struct qed_iwarp_accept_in *iparams); |
|
|
|
int (*iwarp_reject)(void *rdma_cxt, |
|
struct qed_iwarp_reject_in *iparams); |
|
|
|
int (*iwarp_destroy_listen)(void *rdma_cxt, void *handle); |
|
|
|
int (*iwarp_send_rtr)(void *rdma_cxt, |
|
struct qed_iwarp_send_rtr_in *iparams); |
|
}; |
|
|
|
const struct qed_rdma_ops *qed_get_rdma_ops(void); |
|
|
|
#endif
|
|
|