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295 lines
8.7 KiB
295 lines
8.7 KiB
/* |
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* include/linux/amba/pl022.h |
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* |
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* Copyright (C) 2008-2009 ST-Ericsson AB |
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* Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
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* |
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* Author: Linus Walleij <[email protected]> |
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* |
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* Initial version inspired by: |
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* linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c |
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* Initial adoption to PL022 by: |
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* Sachin Verma <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#ifndef _SSP_PL022_H |
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#define _SSP_PL022_H |
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#include <linux/types.h> |
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/** |
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* whether SSP is in loopback mode or not |
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*/ |
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enum ssp_loopback { |
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LOOPBACK_DISABLED, |
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LOOPBACK_ENABLED |
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}; |
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/** |
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* enum ssp_interface - interfaces allowed for this SSP Controller |
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* @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface |
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* @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial |
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* interface |
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* @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire |
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* interface |
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* @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810 |
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* &STn8815 only) |
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*/ |
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enum ssp_interface { |
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SSP_INTERFACE_MOTOROLA_SPI, |
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SSP_INTERFACE_TI_SYNC_SERIAL, |
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SSP_INTERFACE_NATIONAL_MICROWIRE, |
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SSP_INTERFACE_UNIDIRECTIONAL |
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}; |
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/** |
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* enum ssp_hierarchy - whether SSP is configured as Master or Slave |
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*/ |
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enum ssp_hierarchy { |
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SSP_MASTER, |
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SSP_SLAVE |
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}; |
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/** |
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* enum ssp_clock_params - clock parameters, to set SSP clock at a |
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* desired freq |
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*/ |
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struct ssp_clock_params { |
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u8 cpsdvsr; /* value from 2 to 254 (even only!) */ |
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u8 scr; /* value from 0 to 255 */ |
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}; |
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/** |
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* enum ssp_rx_endian - endianess of Rx FIFO Data |
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* this feature is only available in ST versionf of PL022 |
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*/ |
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enum ssp_rx_endian { |
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SSP_RX_MSB, |
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SSP_RX_LSB |
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}; |
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/** |
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* enum ssp_tx_endian - endianess of Tx FIFO Data |
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*/ |
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enum ssp_tx_endian { |
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SSP_TX_MSB, |
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SSP_TX_LSB |
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}; |
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/** |
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* enum ssp_data_size - number of bits in one data element |
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*/ |
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enum ssp_data_size { |
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SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6, |
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SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9, |
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SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12, |
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SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15, |
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SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18, |
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SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21, |
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SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24, |
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SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27, |
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SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30, |
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SSP_DATA_BITS_31, SSP_DATA_BITS_32 |
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}; |
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/** |
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* enum ssp_mode - SSP mode of operation (Communication modes) |
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*/ |
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enum ssp_mode { |
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INTERRUPT_TRANSFER, |
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POLLING_TRANSFER, |
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DMA_TRANSFER |
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}; |
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/** |
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* enum ssp_rx_level_trig - receive FIFO watermark level which triggers |
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* IT: Interrupt fires when _N_ or more elements in RX FIFO. |
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*/ |
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enum ssp_rx_level_trig { |
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SSP_RX_1_OR_MORE_ELEM, |
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SSP_RX_4_OR_MORE_ELEM, |
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SSP_RX_8_OR_MORE_ELEM, |
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SSP_RX_16_OR_MORE_ELEM, |
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SSP_RX_32_OR_MORE_ELEM |
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}; |
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/** |
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* Transmit FIFO watermark level which triggers (IT Interrupt fires |
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* when _N_ or more empty locations in TX FIFO) |
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*/ |
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enum ssp_tx_level_trig { |
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SSP_TX_1_OR_MORE_EMPTY_LOC, |
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SSP_TX_4_OR_MORE_EMPTY_LOC, |
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SSP_TX_8_OR_MORE_EMPTY_LOC, |
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SSP_TX_16_OR_MORE_EMPTY_LOC, |
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SSP_TX_32_OR_MORE_EMPTY_LOC |
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}; |
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/** |
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* enum SPI Clock Phase - clock phase (Motorola SPI interface only) |
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* @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity) |
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* @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity) |
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*/ |
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enum ssp_spi_clk_phase { |
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SSP_CLK_FIRST_EDGE, |
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SSP_CLK_SECOND_EDGE |
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}; |
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/** |
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* enum SPI Clock Polarity - clock polarity (Motorola SPI interface only) |
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* @SSP_CLK_POL_IDLE_LOW: Low inactive level |
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* @SSP_CLK_POL_IDLE_HIGH: High inactive level |
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*/ |
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enum ssp_spi_clk_pol { |
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SSP_CLK_POL_IDLE_LOW, |
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SSP_CLK_POL_IDLE_HIGH |
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}; |
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/** |
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* Microwire Conrol Lengths Command size in microwire format |
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*/ |
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enum ssp_microwire_ctrl_len { |
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SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6, |
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SSP_BITS_7, SSP_BITS_8, SSP_BITS_9, |
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SSP_BITS_10, SSP_BITS_11, SSP_BITS_12, |
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SSP_BITS_13, SSP_BITS_14, SSP_BITS_15, |
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SSP_BITS_16, SSP_BITS_17, SSP_BITS_18, |
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SSP_BITS_19, SSP_BITS_20, SSP_BITS_21, |
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SSP_BITS_22, SSP_BITS_23, SSP_BITS_24, |
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SSP_BITS_25, SSP_BITS_26, SSP_BITS_27, |
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SSP_BITS_28, SSP_BITS_29, SSP_BITS_30, |
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SSP_BITS_31, SSP_BITS_32 |
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}; |
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/** |
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* enum Microwire Wait State |
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* @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit |
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* @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit |
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*/ |
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enum ssp_microwire_wait_state { |
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SSP_MWIRE_WAIT_ZERO, |
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SSP_MWIRE_WAIT_ONE |
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}; |
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/** |
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* enum ssp_duplex - whether Full/Half Duplex on microwire, only |
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* available in the ST Micro variant. |
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* @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional, |
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* SSPRXD not used |
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* @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is |
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* an input. |
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*/ |
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enum ssp_duplex { |
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SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
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SSP_MICROWIRE_CHANNEL_HALF_DUPLEX |
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}; |
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/** |
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* enum ssp_clkdelay - an optional clock delay on the feedback clock |
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* only available in the ST Micro PL023 variant. |
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* @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the |
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* slave is sampled directly |
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* @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with |
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* a delay of T-dt |
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* @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt |
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* @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt |
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* @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt |
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* @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt |
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* @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt |
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* @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt |
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*/ |
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enum ssp_clkdelay { |
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SSP_FEEDBACK_CLK_DELAY_NONE, |
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SSP_FEEDBACK_CLK_DELAY_1T, |
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SSP_FEEDBACK_CLK_DELAY_2T, |
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SSP_FEEDBACK_CLK_DELAY_3T, |
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SSP_FEEDBACK_CLK_DELAY_4T, |
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SSP_FEEDBACK_CLK_DELAY_5T, |
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SSP_FEEDBACK_CLK_DELAY_6T, |
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SSP_FEEDBACK_CLK_DELAY_7T |
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}; |
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/** |
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* CHIP select/deselect commands |
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*/ |
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enum ssp_chip_select { |
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SSP_CHIP_SELECT, |
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SSP_CHIP_DESELECT |
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}; |
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struct dma_chan; |
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/** |
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* struct pl022_ssp_master - device.platform_data for SPI controller devices. |
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* @bus_id: identifier for this bus |
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* @num_chipselect: chipselects are used to distinguish individual |
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* SPI slaves, and are numbered from zero to num_chipselects - 1. |
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* each slave has a chipselect signal, but it's common that not |
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* every chipselect is connected to a slave. |
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* @enable_dma: if true enables DMA driven transfers. |
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* @dma_rx_param: parameter to locate an RX DMA channel. |
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* @dma_tx_param: parameter to locate a TX DMA channel. |
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* @autosuspend_delay: delay in ms following transfer completion before the |
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* runtime power management system suspends the device. A setting of 0 |
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* indicates no delay and the device will be suspended immediately. |
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* @rt: indicates the controller should run the message pump with realtime |
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* priority to minimise the transfer latency on the bus. |
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* @chipselects: list of <num_chipselects> chip select gpios |
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*/ |
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struct pl022_ssp_controller { |
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u16 bus_id; |
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u8 num_chipselect; |
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u8 enable_dma:1; |
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bool (*dma_filter)(struct dma_chan *chan, void *filter_param); |
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void *dma_rx_param; |
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void *dma_tx_param; |
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int autosuspend_delay; |
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bool rt; |
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int *chipselects; |
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}; |
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/** |
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* struct ssp_config_chip - spi_board_info.controller_data for SPI |
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* slave devices, copied to spi_device.controller_data. |
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* |
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* @iface: Interface type(Motorola, TI, Microwire, Universal) |
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* @hierarchy: sets whether interface is master or slave |
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* @slave_tx_disable: SSPTXD is disconnected (in slave mode only) |
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* @clk_freq: Tune freq parameters of SSP(when in master mode) |
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* @com_mode: communication mode: polling, Interrupt or DMA |
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* @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode) |
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* @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode) |
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* @ctrl_len: Microwire interface: Control length |
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* @wait_state: Microwire interface: Wait state |
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* @duplex: Microwire interface: Full/Half duplex |
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* @clkdelay: on the PL023 variant, the delay in feeback clock cycles |
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* before sampling the incoming line |
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* @cs_control: function pointer to board-specific function to |
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* assert/deassert I/O port to control HW generation of devices chip-select. |
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*/ |
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struct pl022_config_chip { |
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enum ssp_interface iface; |
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enum ssp_hierarchy hierarchy; |
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bool slave_tx_disable; |
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struct ssp_clock_params clk_freq; |
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enum ssp_mode com_mode; |
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enum ssp_rx_level_trig rx_lev_trig; |
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enum ssp_tx_level_trig tx_lev_trig; |
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enum ssp_microwire_ctrl_len ctrl_len; |
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enum ssp_microwire_wait_state wait_state; |
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enum ssp_duplex duplex; |
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enum ssp_clkdelay clkdelay; |
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void (*cs_control) (u32 control); |
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}; |
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#endif /* _SSP_PL022_H */
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