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195 lines
5.4 KiB
195 lines
5.4 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2013 Altera Corporation |
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* Copyright (C) 2011 Tobias Klauser <[email protected]> |
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* |
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* Based on cpuinfo.c from microblaze |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/delay.h> |
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#include <linux/seq_file.h> |
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#include <linux/string.h> |
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#include <linux/of.h> |
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#include <asm/cpuinfo.h> |
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struct cpuinfo cpuinfo; |
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#define err_cpu(x) \ |
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pr_err("ERROR: Nios II " x " different for kernel and DTS\n") |
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static inline u32 fcpu(struct device_node *cpu, const char *n) |
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{ |
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u32 val = 0; |
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of_property_read_u32(cpu, n, &val); |
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return val; |
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} |
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void __init setup_cpuinfo(void) |
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{ |
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struct device_node *cpu; |
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const char *str; |
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int len; |
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cpu = of_get_cpu_node(0, NULL); |
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if (!cpu) |
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panic("%s: No CPU found in devicetree!\n", __func__); |
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if (!of_property_read_bool(cpu, "altr,has-initda")) |
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panic("initda instruction is unimplemented. Please update your " |
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"hardware system to have more than 4-byte line data " |
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"cache\n"); |
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cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); |
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str = of_get_property(cpu, "altr,implementation", &len); |
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if (str) |
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strlcpy(cpuinfo.cpu_impl, str, sizeof(cpuinfo.cpu_impl)); |
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else |
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strcpy(cpuinfo.cpu_impl, "<unknown>"); |
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cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); |
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cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); |
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cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); |
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cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); |
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cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); |
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cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); |
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if (IS_ENABLED(CONFIG_NIOS2_HW_DIV_SUPPORT) && !cpuinfo.has_div) |
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err_cpu("DIV"); |
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if (IS_ENABLED(CONFIG_NIOS2_HW_MUL_SUPPORT) && !cpuinfo.has_mul) |
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err_cpu("MUL"); |
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if (IS_ENABLED(CONFIG_NIOS2_HW_MULX_SUPPORT) && !cpuinfo.has_mulx) |
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err_cpu("MULX"); |
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if (IS_ENABLED(CONFIG_NIOS2_BMX_SUPPORT) && !cpuinfo.has_bmx) |
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err_cpu("BMX"); |
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if (IS_ENABLED(CONFIG_NIOS2_CDX_SUPPORT) && !cpuinfo.has_cdx) |
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err_cpu("CDX"); |
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cpuinfo.tlb_num_ways = fcpu(cpu, "altr,tlb-num-ways"); |
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if (!cpuinfo.tlb_num_ways) |
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panic("altr,tlb-num-ways can't be 0. Please check your hardware " |
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"system\n"); |
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cpuinfo.icache_line_size = fcpu(cpu, "icache-line-size"); |
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cpuinfo.icache_size = fcpu(cpu, "icache-size"); |
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if (CONFIG_NIOS2_ICACHE_SIZE != cpuinfo.icache_size) |
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pr_warn("Warning: icache size configuration mismatch " |
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"(0x%x vs 0x%x) of CONFIG_NIOS2_ICACHE_SIZE vs " |
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"device tree icache-size\n", |
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CONFIG_NIOS2_ICACHE_SIZE, cpuinfo.icache_size); |
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cpuinfo.dcache_line_size = fcpu(cpu, "dcache-line-size"); |
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if (CONFIG_NIOS2_DCACHE_LINE_SIZE != cpuinfo.dcache_line_size) |
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pr_warn("Warning: dcache line size configuration mismatch " |
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"(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_LINE_SIZE vs " |
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"device tree dcache-line-size\n", |
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CONFIG_NIOS2_DCACHE_LINE_SIZE, cpuinfo.dcache_line_size); |
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cpuinfo.dcache_size = fcpu(cpu, "dcache-size"); |
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if (CONFIG_NIOS2_DCACHE_SIZE != cpuinfo.dcache_size) |
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pr_warn("Warning: dcache size configuration mismatch " |
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"(0x%x vs 0x%x) of CONFIG_NIOS2_DCACHE_SIZE vs " |
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"device tree dcache-size\n", |
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CONFIG_NIOS2_DCACHE_SIZE, cpuinfo.dcache_size); |
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cpuinfo.tlb_pid_num_bits = fcpu(cpu, "altr,pid-num-bits"); |
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cpuinfo.tlb_num_ways_log2 = ilog2(cpuinfo.tlb_num_ways); |
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cpuinfo.tlb_num_entries = fcpu(cpu, "altr,tlb-num-entries"); |
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cpuinfo.tlb_num_lines = cpuinfo.tlb_num_entries / cpuinfo.tlb_num_ways; |
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cpuinfo.tlb_ptr_sz = fcpu(cpu, "altr,tlb-ptr-sz"); |
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cpuinfo.reset_addr = fcpu(cpu, "altr,reset-addr"); |
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cpuinfo.exception_addr = fcpu(cpu, "altr,exception-addr"); |
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cpuinfo.fast_tlb_miss_exc_addr = fcpu(cpu, "altr,fast-tlb-miss-addr"); |
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of_node_put(cpu); |
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} |
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#ifdef CONFIG_PROC_FS |
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/* |
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* Get CPU information for use by the procfs. |
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*/ |
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static int show_cpuinfo(struct seq_file *m, void *v) |
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{ |
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const u32 clockfreq = cpuinfo.cpu_clock_freq; |
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seq_printf(m, |
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"CPU:\t\tNios II/%s\n" |
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"REV:\t\t%i\n" |
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"MMU:\t\t%s\n" |
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"FPU:\t\tnone\n" |
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"Clocking:\t%u.%02u MHz\n" |
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"BogoMips:\t%lu.%02lu\n" |
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"Calibration:\t%lu loops\n", |
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cpuinfo.cpu_impl, |
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CONFIG_NIOS2_ARCH_REVISION, |
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cpuinfo.mmu ? "present" : "none", |
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clockfreq / 1000000, (clockfreq / 100000) % 10, |
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(loops_per_jiffy * HZ) / 500000, |
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((loops_per_jiffy * HZ) / 5000) % 100, |
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(loops_per_jiffy * HZ)); |
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seq_printf(m, |
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"HW:\n" |
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" MUL:\t\t%s\n" |
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" MULX:\t\t%s\n" |
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" DIV:\t\t%s\n" |
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" BMX:\t\t%s\n" |
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" CDX:\t\t%s\n", |
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cpuinfo.has_mul ? "yes" : "no", |
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cpuinfo.has_mulx ? "yes" : "no", |
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cpuinfo.has_div ? "yes" : "no", |
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cpuinfo.has_bmx ? "yes" : "no", |
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cpuinfo.has_cdx ? "yes" : "no"); |
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seq_printf(m, |
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"Icache:\t\t%ukB, line length: %u\n", |
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cpuinfo.icache_size >> 10, |
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cpuinfo.icache_line_size); |
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seq_printf(m, |
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"Dcache:\t\t%ukB, line length: %u\n", |
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cpuinfo.dcache_size >> 10, |
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cpuinfo.dcache_line_size); |
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seq_printf(m, |
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"TLB:\t\t%u ways, %u entries, %u PID bits\n", |
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cpuinfo.tlb_num_ways, |
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cpuinfo.tlb_num_entries, |
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cpuinfo.tlb_pid_num_bits); |
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return 0; |
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} |
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static void *cpuinfo_start(struct seq_file *m, loff_t *pos) |
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{ |
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unsigned long i = *pos; |
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return i < num_possible_cpus() ? (void *) (i + 1) : NULL; |
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} |
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static void *cpuinfo_next(struct seq_file *m, void *v, loff_t *pos) |
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{ |
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++*pos; |
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return cpuinfo_start(m, pos); |
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} |
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static void cpuinfo_stop(struct seq_file *m, void *v) |
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{ |
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} |
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const struct seq_operations cpuinfo_op = { |
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.start = cpuinfo_start, |
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.next = cpuinfo_next, |
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.stop = cpuinfo_stop, |
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.show = show_cpuinfo |
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}; |
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#endif /* CONFIG_PROC_FS */
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