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29 lines
771 B
29 lines
771 B
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Marvell Tauros3 cache controller includes |
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* |
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* Sebastian Hesselbarth <[email protected]> |
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* |
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* based on GPL'ed 2.6 kernel sources |
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* (c) Marvell International Ltd. |
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*/ |
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#ifndef __ASM_ARM_HARDWARE_TAUROS3_H |
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#define __ASM_ARM_HARDWARE_TAUROS3_H |
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/* |
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* Marvell Tauros3 L2CC is compatible with PL310 r0p0 |
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* but with PREFETCH_CTRL (r2p0) and an additional event counter. |
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* Also, there is AUX2_CTRL for some Marvell specific control. |
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*/ |
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#define TAUROS3_EVENT_CNT2_CFG 0x224 |
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#define TAUROS3_EVENT_CNT2_VAL 0x228 |
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#define TAUROS3_INV_ALL 0x780 |
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#define TAUROS3_CLEAN_ALL 0x784 |
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#define TAUROS3_AUX2_CTRL 0x820 |
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/* Registers shifts and masks */ |
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#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2) |
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#endif
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