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63 lines
1.3 KiB
63 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* sleep mode for CSR SiRFprimaII |
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* |
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
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*/ |
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#include <linux/linkage.h> |
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#include <asm/ptrace.h> |
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#include <asm/assembler.h> |
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#include "pm.h" |
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#define DENALI_CTL_22_OFF 0x58 |
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#define DENALI_CTL_112_OFF 0x1c0 |
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.text |
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ENTRY(sirfsoc_finish_suspend) |
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@ r5: mem controller |
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ldr r0, =sirfsoc_memc_base |
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ldr r5, [r0] |
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@ r6: pwrc base offset |
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ldr r0, =sirfsoc_pwrc_base |
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ldr r6, [r0] |
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@ r7: rtc iobrg controller |
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ldr r0, =sirfsoc_rtciobrg_base |
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ldr r7, [r0] |
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@ Read the power control register and set the |
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@ sleep force bit. |
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add r0, r6, #SIRFSOC_PWRC_PDN_CTRL |
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bl __sirfsoc_rtc_iobrg_readl |
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orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE |
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add r1, r6, #SIRFSOC_PWRC_PDN_CTRL |
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bl sirfsoc_rtc_iobrg_pre_writel |
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mov r1, #0x1 |
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@ read the MEM ctl register and set the self |
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@ refresh bit |
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ldr r2, [r5, #DENALI_CTL_22_OFF] |
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orr r2, r2, #0x1 |
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@ Following code has to run from cache since |
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@ the RAM is going to self refresh mode |
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.align 5 |
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str r2, [r5, #DENALI_CTL_22_OFF] |
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1: |
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ldr r4, [r5, #DENALI_CTL_112_OFF] |
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tst r4, #0x1 |
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bne 1b |
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@ write SLEEPFORCE through rtc iobridge |
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str r1, [r7] |
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@ wait rtc io bridge sync |
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1: |
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ldr r3, [r7] |
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tst r3, #0x01 |
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bne 1b |
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b .
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