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163 lines
3.5 KiB
163 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* platform device definitions for the iop3xx dma/xor engines |
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* Copyright © 2006, Intel Corporation. |
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*/ |
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#include <linux/platform_device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/platform_data/dma-iop32x.h> |
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#include "iop3xx.h" |
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#include "irqs.h" |
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#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT |
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#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC |
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#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR |
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#define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT |
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#define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC |
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#define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR |
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#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT |
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#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC |
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#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR |
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/* AAU and DMA Channels */ |
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static struct resource iop3xx_dma_0_resources[] = { |
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[0] = { |
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.start = IOP3XX_DMA_PHYS_BASE(0), |
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.end = IOP3XX_DMA_UPPER_PA(0), |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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.start = IRQ_DMA0_EOT, |
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.end = IRQ_DMA0_EOT, |
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.flags = IORESOURCE_IRQ |
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}, |
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[2] = { |
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.start = IRQ_DMA0_EOC, |
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.end = IRQ_DMA0_EOC, |
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.flags = IORESOURCE_IRQ |
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}, |
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[3] = { |
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.start = IRQ_DMA0_ERR, |
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.end = IRQ_DMA0_ERR, |
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.flags = IORESOURCE_IRQ |
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} |
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}; |
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static struct resource iop3xx_dma_1_resources[] = { |
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[0] = { |
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.start = IOP3XX_DMA_PHYS_BASE(1), |
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.end = IOP3XX_DMA_UPPER_PA(1), |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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.start = IRQ_DMA1_EOT, |
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.end = IRQ_DMA1_EOT, |
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.flags = IORESOURCE_IRQ |
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}, |
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[2] = { |
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.start = IRQ_DMA1_EOC, |
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.end = IRQ_DMA1_EOC, |
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.flags = IORESOURCE_IRQ |
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}, |
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[3] = { |
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.start = IRQ_DMA1_ERR, |
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.end = IRQ_DMA1_ERR, |
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.flags = IORESOURCE_IRQ |
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} |
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}; |
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static struct resource iop3xx_aau_resources[] = { |
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[0] = { |
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.start = IOP3XX_AAU_PHYS_BASE, |
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.end = IOP3XX_AAU_UPPER_PA, |
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.flags = IORESOURCE_MEM, |
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}, |
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[1] = { |
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.start = IRQ_AA_EOT, |
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.end = IRQ_AA_EOT, |
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.flags = IORESOURCE_IRQ |
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}, |
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[2] = { |
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.start = IRQ_AA_EOC, |
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.end = IRQ_AA_EOC, |
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.flags = IORESOURCE_IRQ |
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}, |
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[3] = { |
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.start = IRQ_AA_ERR, |
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.end = IRQ_AA_ERR, |
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.flags = IORESOURCE_IRQ |
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} |
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}; |
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static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32); |
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static struct iop_adma_platform_data iop3xx_dma_0_data = { |
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.hw_id = DMA0_ID, |
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.pool_size = PAGE_SIZE, |
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}; |
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static struct iop_adma_platform_data iop3xx_dma_1_data = { |
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.hw_id = DMA1_ID, |
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.pool_size = PAGE_SIZE, |
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}; |
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static struct iop_adma_platform_data iop3xx_aau_data = { |
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.hw_id = AAU_ID, |
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.pool_size = 3 * PAGE_SIZE, |
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}; |
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struct platform_device iop3xx_dma_0_channel = { |
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.name = "iop-adma", |
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.id = 0, |
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.num_resources = 4, |
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.resource = iop3xx_dma_0_resources, |
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.dev = { |
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.dma_mask = &iop3xx_adma_dmamask, |
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.coherent_dma_mask = DMA_BIT_MASK(32), |
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.platform_data = (void *) &iop3xx_dma_0_data, |
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}, |
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}; |
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struct platform_device iop3xx_dma_1_channel = { |
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.name = "iop-adma", |
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.id = 1, |
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.num_resources = 4, |
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.resource = iop3xx_dma_1_resources, |
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.dev = { |
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.dma_mask = &iop3xx_adma_dmamask, |
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.coherent_dma_mask = DMA_BIT_MASK(32), |
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.platform_data = (void *) &iop3xx_dma_1_data, |
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}, |
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}; |
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struct platform_device iop3xx_aau_channel = { |
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.name = "iop-adma", |
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.id = 2, |
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.num_resources = 4, |
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.resource = iop3xx_aau_resources, |
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.dev = { |
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.dma_mask = &iop3xx_adma_dmamask, |
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.coherent_dma_mask = DMA_BIT_MASK(32), |
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.platform_data = (void *) &iop3xx_aau_data, |
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}, |
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}; |
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static int __init iop3xx_adma_cap_init(void) |
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{ |
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dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); |
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dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); |
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dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); |
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dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); |
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dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); |
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dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); |
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return 0; |
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} |
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arch_initcall(iop3xx_adma_cap_init);
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