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647 lines
20 KiB
647 lines
20 KiB
#include <mcu/stm32.h> |
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#include <mcu/cortex-m.h> |
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#define CRC_CR_RESET 0x00000001 |
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struct CRC { |
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volatile uint32_t DR; |
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volatile uint8_t IDR; |
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uint8_t RESERVED0; |
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uint16_t RESERVED1; |
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volatile uint32_t CR; |
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}; |
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#define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
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static struct CRC *const CRC = (struct CRC *)CRC_BASE; |
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struct ADC { |
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volatile uint32_t SR; |
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volatile uint32_t CR1; |
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volatile uint32_t CR2; |
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volatile uint32_t SMPR1; |
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volatile uint32_t SMPR2; |
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volatile uint32_t JOFR1; |
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volatile uint32_t JOFR2; |
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volatile uint32_t JOFR3; |
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volatile uint32_t JOFR4; |
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volatile uint32_t HTR; |
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volatile uint32_t LTR; |
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volatile uint32_t SQR1; |
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volatile uint32_t SQR2; |
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volatile uint32_t SQR3; |
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volatile uint32_t JSQR; |
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volatile uint32_t JDR1; |
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volatile uint32_t JDR2; |
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volatile uint32_t JDR3; |
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volatile uint32_t JDR4; |
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volatile uint32_t DR; |
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}; |
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#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
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#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
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static struct ADC *const ADC1 = (struct ADC *)ADC1_BASE; |
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static struct ADC *const ADC2 = (struct ADC *)ADC2_BASE; |
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#define ADC_CR1_DUALMOD_0 0x00010000 |
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#define ADC_CR1_DUALMOD_1 0x00020000 |
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#define ADC_CR1_DUALMOD_2 0x00040000 |
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#define ADC_CR1_DUALMOD_3 0x00080000 |
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#define ADC_CR1_SCAN 0x00000100 |
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#define ADC_CR2_ADON 0x00000001 |
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#define ADC_CR2_CONT 0x00000002 |
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#define ADC_CR2_CAL 0x00000004 |
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#define ADC_CR2_RSTCAL 0x00000008 |
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#define ADC_CR2_DMA 0x00000100 |
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#define ADC_CR2_ALIGN 0x00000800 |
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#define ADC_CR2_EXTSEL 0x000E0000 |
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#define ADC_CR2_EXTSEL_0 0x00020000 |
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#define ADC_CR2_EXTSEL_1 0x00040000 |
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#define ADC_CR2_EXTSEL_2 0x00080000 |
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#define ADC_CR2_EXTTRIG 0x00100000 |
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#define ADC_CR2_SWSTART 0x00400000 |
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#define ADC_CR2_TSVREFE 0x00800000 |
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struct DMA_Channel { |
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volatile uint32_t CCR; |
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volatile uint32_t CNDTR; |
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volatile uint32_t CPAR; |
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volatile uint32_t CMAR; |
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}; |
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struct DMA { |
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volatile uint32_t ISR; |
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volatile uint32_t IFCR; |
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}; |
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#define STM32_DMA_CR_MINC DMA_CCR1_MINC |
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#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1 |
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#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1 |
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#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE |
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#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE |
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#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE |
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#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1 |
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#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1 |
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#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1 |
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#define STM32_DMA_ISR_MASK 0x0F |
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#define STM32_DMA_CCR_RESET_VALUE 0x00000000 |
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#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL |
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#define STM32_DMA_CR_PL(n) ((n) << 12) |
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#define DMA_CCR1_EN 0x00000001 |
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#define DMA_CCR1_TCIE 0x00000002 |
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#define DMA_CCR1_HTIE 0x00000004 |
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#define DMA_CCR1_TEIE 0x00000008 |
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#define DMA_CCR1_DIR 0x00000010 |
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#define DMA_CCR1_CIRC 0x00000020 |
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#define DMA_CCR1_PINC 0x00000040 |
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#define DMA_CCR1_MINC 0x00000080 |
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#define DMA_CCR1_PSIZE 0x00000300 |
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#define DMA_CCR1_PSIZE_0 0x00000100 |
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#define DMA_CCR1_PSIZE_1 0x00000200 |
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#define DMA_CCR1_MSIZE 0x00000C00 |
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#define DMA_CCR1_MSIZE_0 0x00000400 |
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#define DMA_CCR1_MSIZE_1 0x00000800 |
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#define DMA_CCR1_PL 0x00003000 |
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#define DMA_CCR1_PL_0 0x00001000 |
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#define DMA_CCR1_PL_1 0x00002000 |
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#define DMA_CCR1_MEM2MEM 0x00004000 |
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#define DMA_ISR_GIF1 0x00000001 |
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#define DMA_ISR_TCIF1 0x00000002 |
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#define DMA_ISR_HTIF1 0x00000004 |
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#define DMA_ISR_TEIF1 0x00000008 |
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#define DMA_ISR_GIF2 0x00000010 |
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#define DMA_ISR_TCIF2 0x00000020 |
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#define DMA_ISR_HTIF2 0x00000040 |
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#define DMA_ISR_TEIF2 0x00000080 |
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#define DMA_ISR_GIF3 0x00000100 |
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#define DMA_ISR_TCIF3 0x00000200 |
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#define DMA_ISR_HTIF3 0x00000400 |
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#define DMA_ISR_TEIF3 0x00000800 |
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#define DMA_ISR_GIF4 0x00001000 |
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#define DMA_ISR_TCIF4 0x00002000 |
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#define DMA_ISR_HTIF4 0x00004000 |
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#define DMA_ISR_TEIF4 0x00008000 |
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#define DMA_ISR_GIF5 0x00010000 |
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#define DMA_ISR_TCIF5 0x00020000 |
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#define DMA_ISR_HTIF5 0x00040000 |
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#define DMA_ISR_TEIF5 0x00080000 |
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#define DMA_ISR_GIF6 0x00100000 |
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#define DMA_ISR_TCIF6 0x00200000 |
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#define DMA_ISR_HTIF6 0x00400000 |
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#define DMA_ISR_TEIF6 0x00800000 |
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#define DMA_ISR_GIF7 0x01000000 |
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#define DMA_ISR_TCIF7 0x02000000 |
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#define DMA_ISR_HTIF7 0x04000000 |
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#define DMA_ISR_TEIF7 0x08000000 |
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#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
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static struct DMA *const DMA1 = (struct DMA *)DMA1_BASE; |
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#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
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static struct DMA_Channel *const DMA1_Channel1 = |
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(struct DMA_Channel *)DMA1_Channel1_BASE; |
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/* Timer */ |
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struct TIM |
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{ |
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volatile uint16_t CR1; uint16_t RESERVED0; |
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volatile uint16_t CR2; uint16_t RESERVED1; |
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volatile uint16_t SMCR; uint16_t RESERVED2; |
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volatile uint16_t DIER; uint16_t RESERVED3; |
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volatile uint16_t SR; uint16_t RESERVED4; |
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volatile uint16_t EGR; uint16_t RESERVED5; |
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volatile uint16_t CCMR1; uint16_t RESERVED6; |
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volatile uint16_t CCMR2; uint16_t RESERVED7; |
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volatile uint16_t CCER; uint16_t RESERVED8; |
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volatile uint16_t CNT; uint16_t RESERVED9; |
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volatile uint16_t PSC; uint16_t RESERVED10; |
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volatile uint16_t ARR; uint16_t RESERVED11; |
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volatile uint16_t RCR; uint16_t RESERVED12; |
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volatile uint16_t CCR1; uint16_t RESERVED13; |
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volatile uint16_t CCR2; uint16_t RESERVED14; |
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volatile uint16_t CCR3; uint16_t RESERVED15; |
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volatile uint16_t CCR4; uint16_t RESERVED16; |
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volatile uint16_t BDTR; uint16_t RESERVED17; |
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volatile uint16_t DCR; uint16_t RESERVED18; |
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volatile uint16_t DMAR; uint16_t RESERVED19; |
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}; |
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#define TIM2_BASE 0x40000000 |
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#define TIM3_BASE 0x40000400 |
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#define TIM4_BASE 0x40000800 |
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static struct TIM *const TIM2 = (struct TIM *)TIM2_BASE; |
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static struct TIM *const TIM3 = (struct TIM *)TIM3_BASE; |
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static struct TIM *const TIM4 = (struct TIM *)TIM4_BASE; |
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#define TIM_CR1_CEN 0x0001 |
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#define TIM_CR1_UDIS 0x0002 |
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#define TIM_CR1_URS 0x0004 |
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#define TIM_CR1_OPM 0x0008 |
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#define TIM_CR1_DIR 0x0010 |
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#define TIM_CR1_CMS 0x0060 |
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#define TIM_CR1_CMS_0 0x0020 |
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#define TIM_CR1_CMS_1 0x0040 |
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#define TIM_CR1_ARPE 0x0080 |
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#define TIM_CR1_CKD 0x0300 |
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#define TIM_CR1_CKD_0 0x0100 |
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#define TIM_CR1_CKD_1 0x0200 |
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#define TIM_CR2_CCPC 0x0001 |
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#define TIM_CR2_CCUS 0x0004 |
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#define TIM_CR2_CCDS 0x0008 |
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#define TIM_CR2_MMS 0x0070 |
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#define TIM_CR2_MMS_0 0x0010 |
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#define TIM_CR2_MMS_1 0x0020 |
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#define TIM_CR2_MMS_2 0x0040 |
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#define TIM_CR2_TI1S 0x0080 |
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#define TIM_CR2_OIS1 0x0100 |
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#define TIM_CR2_OIS1N 0x0200 |
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#define TIM_CR2_OIS2 0x0400 |
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#define TIM_CR2_OIS2N 0x0800 |
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#define TIM_CR2_OIS3 0x1000 |
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#define TIM_CR2_OIS3N 0x2000 |
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#define TIM_CR2_OIS4 0x4000 |
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#define TIM_SMCR_SMS 0x0007 |
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#define TIM_SMCR_SMS_0 0x0001 |
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#define TIM_SMCR_SMS_1 0x0002 |
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#define TIM_SMCR_SMS_2 0x0004 |
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#define TIM_SMCR_TS 0x0070 |
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#define TIM_SMCR_TS_0 0x0010 |
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#define TIM_SMCR_TS_1 0x0020 |
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#define TIM_SMCR_TS_2 0x0040 |
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#define TIM_SMCR_MSM 0x0080 |
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#define TIM_SMCR_ETF 0x0F00 |
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#define TIM_SMCR_ETF_0 0x0100 |
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#define TIM_SMCR_ETF_1 0x0200 |
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#define TIM_SMCR_ETF_2 0x0400 |
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#define TIM_SMCR_ETF_3 0x0800 |
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#define TIM_SMCR_ETPS 0x3000 |
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#define TIM_SMCR_ETPS_0 0x1000 |
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#define TIM_SMCR_ETPS_1 0x2000 |
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#define TIM_SMCR_ECE 0x4000 |
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#define TIM_SMCR_ETP 0x8000 |
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#define TIM_DIER_UIE 0x0001 |
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#define TIM_DIER_CC1IE 0x0002 |
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#define TIM_DIER_CC2IE 0x0004 |
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#define TIM_DIER_CC3IE 0x0008 |
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#define TIM_DIER_CC4IE 0x0010 |
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#define TIM_DIER_COMIE 0x0020 |
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#define TIM_DIER_TIE 0x0040 |
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#define TIM_DIER_BIE 0x0080 |
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#define TIM_DIER_UDE 0x0100 |
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#define TIM_DIER_CC1DE 0x0200 |
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#define TIM_DIER_CC2DE 0x0400 |
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#define TIM_DIER_CC3DE 0x0800 |
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#define TIM_DIER_CC4DE 0x1000 |
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#define TIM_DIER_COMDE 0x2000 |
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#define TIM_DIER_TDE 0x4000 |
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#define TIM_SR_UIF 0x0001 |
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#define TIM_SR_CC1IF 0x0002 |
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#define TIM_SR_CC2IF 0x0004 |
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#define TIM_SR_CC3IF 0x0008 |
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#define TIM_SR_CC4IF 0x0010 |
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#define TIM_SR_COMIF 0x0020 |
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#define TIM_SR_TIF 0x0040 |
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#define TIM_SR_BIF 0x0080 |
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#define TIM_SR_CC1OF 0x0200 |
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#define TIM_SR_CC2OF 0x0400 |
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#define TIM_SR_CC3OF 0x0800 |
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#define TIM_SR_CC4OF 0x1000 |
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#define TIM_EGR_UG 0x01 |
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#define TIM_EGR_CC1G 0x02 |
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#define TIM_EGR_CC2G 0x04 |
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#define TIM_EGR_CC3G 0x08 |
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#define TIM_EGR_CC4G 0x10 |
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#define TIM_EGR_COMG 0x20 |
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#define TIM_EGR_TG 0x40 |
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#define TIM_EGR_BG 0x80 |
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#define TIM_CCMR1_CC1S 0x0003 |
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#define TIM_CCMR1_CC1S_0 0x0001 |
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#define TIM_CCMR1_CC1S_1 0x0002 |
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#define TIM_CCMR1_OC1FE 0x0004 |
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#define TIM_CCMR1_OC1PE 0x0008 |
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#define TIM_CCMR1_OC1M 0x0070 |
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#define TIM_CCMR1_OC1M_0 0x0010 |
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#define TIM_CCMR1_OC1M_1 0x0020 |
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#define TIM_CCMR1_OC1M_2 0x0040 |
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#define TIM_CCMR1_OC1CE 0x0080 |
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#define TIM_CCMR1_CC2S 0x0300 |
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#define TIM_CCMR1_CC2S_0 0x0100 |
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#define TIM_CCMR1_CC2S_1 0x0200 |
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#define TIM_CCMR1_OC2FE 0x0400 |
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#define TIM_CCMR1_OC2PE 0x0800 |
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#define TIM_CCMR1_OC2M 0x7000 |
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#define TIM_CCMR1_OC2M_0 0x1000 |
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#define TIM_CCMR1_OC2M_1 0x2000 |
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#define TIM_CCMR1_OC2M_2 0x4000 |
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#define TIM_CCMR1_OC2CE 0x8000 |
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#define TIM_CCMR1_IC1PSC 0x000C |
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#define TIM_CCMR1_IC1PSC_0 0x0004 |
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#define TIM_CCMR1_IC1PSC_1 0x0008 |
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#define TIM_CCMR1_IC1F 0x00F0 |
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#define TIM_CCMR1_IC1F_0 0x0010 |
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#define TIM_CCMR1_IC1F_1 0x0020 |
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#define TIM_CCMR1_IC1F_2 0x0040 |
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#define TIM_CCMR1_IC1F_3 0x0080 |
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#define TIM_CCMR1_IC2PSC 0x0C00 |
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#define TIM_CCMR1_IC2PSC_0 0x0400 |
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#define TIM_CCMR1_IC2PSC_1 0x0800 |
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#define TIM_CCMR1_IC2F 0xF000 |
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#define TIM_CCMR1_IC2F_0 0x1000 |
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#define TIM_CCMR1_IC2F_1 0x2000 |
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#define TIM_CCMR1_IC2F_2 0x4000 |
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#define TIM_CCMR1_IC2F_3 0x8000 |
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#define TIM_CCMR2_CC3S 0x0003 |
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#define TIM_CCMR2_CC3S_0 0x0001 |
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#define TIM_CCMR2_CC3S_1 0x0002 |
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#define TIM_CCMR2_OC3FE 0x0004 |
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#define TIM_CCMR2_OC3PE 0x0008 |
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#define TIM_CCMR2_OC3M 0x0070 |
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#define TIM_CCMR2_OC3M_0 0x0010 |
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#define TIM_CCMR2_OC3M_1 0x0020 |
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#define TIM_CCMR2_OC3M_2 0x0040 |
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#define TIM_CCMR2_OC3CE 0x0080 |
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#define TIM_CCMR2_CC4S 0x0300 |
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#define TIM_CCMR2_CC4S_0 0x0100 |
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#define TIM_CCMR2_CC4S_1 0x0200 |
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#define TIM_CCMR2_OC4FE 0x0400 |
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#define TIM_CCMR2_OC4PE 0x0800 |
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#define TIM_CCMR2_OC4M 0x7000 |
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#define TIM_CCMR2_OC4M_0 0x1000 |
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#define TIM_CCMR2_OC4M_1 0x2000 |
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#define TIM_CCMR2_OC4M_2 0x4000 |
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#define TIM_CCMR2_OC4CE 0x8000 |
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#define TIM_CCMR2_IC3PSC 0x000C |
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#define TIM_CCMR2_IC3PSC_0 0x0004 |
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#define TIM_CCMR2_IC3PSC_1 0x0008 |
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#define TIM_CCMR2_IC3F 0x00F0 |
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#define TIM_CCMR2_IC3F_0 0x0010 |
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#define TIM_CCMR2_IC3F_1 0x0020 |
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#define TIM_CCMR2_IC3F_2 0x0040 |
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#define TIM_CCMR2_IC3F_3 0x0080 |
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#define TIM_CCMR2_IC4PSC 0x0C00 |
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#define TIM_CCMR2_IC4PSC_0 0x0400 |
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#define TIM_CCMR2_IC4PSC_1 0x0800 |
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#define TIM_CCMR2_IC4F 0xF000 |
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#define TIM_CCMR2_IC4F_0 0x1000 |
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#define TIM_CCMR2_IC4F_1 0x2000 |
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#define TIM_CCMR2_IC4F_2 0x4000 |
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#define TIM_CCMR2_IC4F_3 0x8000 |
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#define TIM_CCER_CC1E 0x0001 |
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#define TIM_CCER_CC1P 0x0002 |
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#define TIM_CCER_CC1NE 0x0004 |
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#define TIM_CCER_CC1NP 0x0008 |
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#define TIM_CCER_CC2E 0x0010 |
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#define TIM_CCER_CC2P 0x0020 |
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#define TIM_CCER_CC2NE 0x0040 |
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#define TIM_CCER_CC2NP 0x0080 |
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#define TIM_CCER_CC3E 0x0100 |
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#define TIM_CCER_CC3P 0x0200 |
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#define TIM_CCER_CC3NE 0x0400 |
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#define TIM_CCER_CC3NP 0x0800 |
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#define TIM_CCER_CC4E 0x1000 |
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#define TIM_CCER_CC4P 0x2000 |
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#define TIM_CNT_CNT 0xFFFF |
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#define TIM_PSC_PSC 0xFFFF |
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#define TIM_ARR_ARR 0xFFFF |
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#define TIM_RCR_REP 0xFF |
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#define TIM_CCR1_CCR1 0xFFFF |
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#define TIM_CCR2_CCR2 0xFFFF |
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#define TIM_CCR3_CCR3 0xFFFF |
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#define TIM_CCR4_CCR4 0xFFFF |
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#define TIM_BDTR_DTG 0x00FF |
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#define TIM_BDTR_DTG_0 0x0001 |
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#define TIM_BDTR_DTG_1 0x0002 |
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#define TIM_BDTR_DTG_2 0x0004 |
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#define TIM_BDTR_DTG_3 0x0008 |
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#define TIM_BDTR_DTG_4 0x0010 |
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#define TIM_BDTR_DTG_5 0x0020 |
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#define TIM_BDTR_DTG_6 0x0040 |
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#define TIM_BDTR_DTG_7 0x0080 |
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#define TIM_BDTR_LOCK 0x0300 |
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#define TIM_BDTR_LOCK_0 0x0100 |
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#define TIM_BDTR_LOCK_1 0x0200 |
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#define TIM_BDTR_OSSI 0x0400 |
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#define TIM_BDTR_OSSR 0x0800 |
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#define TIM_BDTR_BKE 0x1000 |
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#define TIM_BDTR_BKP 0x2000 |
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#define TIM_BDTR_AOE 0x4000 |
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#define TIM_BDTR_MOE 0x8000 |
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#define TIM_DCR_DBA 0x001F |
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#define TIM_DCR_DBA_0 0x0001 |
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#define TIM_DCR_DBA_1 0x0002 |
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#define TIM_DCR_DBA_2 0x0004 |
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#define TIM_DCR_DBA_3 0x0008 |
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#define TIM_DCR_DBA_4 0x0010 |
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#define TIM_DCR_DBL 0x1F00 |
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#define TIM_DCR_DBL_0 0x0100 |
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#define TIM_DCR_DBL_1 0x0200 |
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#define TIM_DCR_DBL_2 0x0400 |
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#define TIM_DCR_DBL_3 0x0800 |
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#define TIM_DCR_DBL_4 0x1000 |
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#define TIM_DMAR_DMAB 0xFFFF |
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struct EXTI |
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{ |
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volatile uint32_t IMR; |
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volatile uint32_t EMR; |
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volatile uint32_t RTSR; |
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volatile uint32_t FTSR; |
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volatile uint32_t SWIER; |
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volatile uint32_t PR; |
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}; |
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#define EXTI_BASE 0x40010400 |
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static struct EXTI *const EXTI = (struct EXTI *)EXTI_BASE; |
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#define EXTI_IMR_MR0 0x00000001 |
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#define EXTI_IMR_MR1 0x00000002 |
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#define EXTI_IMR_MR2 0x00000004 |
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#define EXTI_IMR_MR3 0x00000008 |
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#define EXTI_IMR_MR4 0x00000010 |
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#define EXTI_IMR_MR5 0x00000020 |
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#define EXTI_IMR_MR6 0x00000040 |
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#define EXTI_IMR_MR7 0x00000080 |
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#define EXTI_IMR_MR8 0x00000100 |
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#define EXTI_IMR_MR9 0x00000200 |
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#define EXTI_IMR_MR10 0x00000400 |
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#define EXTI_IMR_MR11 0x00000800 |
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#define EXTI_IMR_MR12 0x00001000 |
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#define EXTI_IMR_MR13 0x00002000 |
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#define EXTI_IMR_MR14 0x00004000 |
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#define EXTI_IMR_MR15 0x00008000 |
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#define EXTI_IMR_MR16 0x00010000 |
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#define EXTI_IMR_MR17 0x00020000 |
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#define EXTI_IMR_MR18 0x00040000 |
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#define EXTI_IMR_MR19 0x00080000 |
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#define EXTI_EMR_MR0 0x00000001 |
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#define EXTI_EMR_MR1 0x00000002 |
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#define EXTI_EMR_MR2 0x00000004 |
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#define EXTI_EMR_MR3 0x00000008 |
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#define EXTI_EMR_MR4 0x00000010 |
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#define EXTI_EMR_MR5 0x00000020 |
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#define EXTI_EMR_MR6 0x00000040 |
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#define EXTI_EMR_MR7 0x00000080 |
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#define EXTI_EMR_MR8 0x00000100 |
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#define EXTI_EMR_MR9 0x00000200 |
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#define EXTI_EMR_MR10 0x00000400 |
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#define EXTI_EMR_MR11 0x00000800 |
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#define EXTI_EMR_MR12 0x00001000 |
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#define EXTI_EMR_MR13 0x00002000 |
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#define EXTI_EMR_MR14 0x00004000 |
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#define EXTI_EMR_MR15 0x00008000 |
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#define EXTI_EMR_MR16 0x00010000 |
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#define EXTI_EMR_MR17 0x00020000 |
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#define EXTI_EMR_MR18 0x00040000 |
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#define EXTI_EMR_MR19 0x00080000 |
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#define EXTI_RTSR_TR0 0x00000001 |
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#define EXTI_RTSR_TR1 0x00000002 |
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#define EXTI_RTSR_TR2 0x00000004 |
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#define EXTI_RTSR_TR3 0x00000008 |
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#define EXTI_RTSR_TR4 0x00000010 |
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#define EXTI_RTSR_TR5 0x00000020 |
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#define EXTI_RTSR_TR6 0x00000040 |
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#define EXTI_RTSR_TR7 0x00000080 |
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#define EXTI_RTSR_TR8 0x00000100 |
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#define EXTI_RTSR_TR9 0x00000200 |
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#define EXTI_RTSR_TR10 0x00000400 |
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#define EXTI_RTSR_TR11 0x00000800 |
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#define EXTI_RTSR_TR12 0x00001000 |
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#define EXTI_RTSR_TR13 0x00002000 |
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#define EXTI_RTSR_TR14 0x00004000 |
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#define EXTI_RTSR_TR15 0x00008000 |
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#define EXTI_RTSR_TR16 0x00010000 |
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#define EXTI_RTSR_TR17 0x00020000 |
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#define EXTI_RTSR_TR18 0x00040000 |
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#define EXTI_RTSR_TR19 0x00080000 |
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#define EXTI_FTSR_TR0 0x00000001 |
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#define EXTI_FTSR_TR1 0x00000002 |
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#define EXTI_FTSR_TR2 0x00000004 |
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#define EXTI_FTSR_TR3 0x00000008 |
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#define EXTI_FTSR_TR4 0x00000010 |
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#define EXTI_FTSR_TR5 0x00000020 |
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#define EXTI_FTSR_TR6 0x00000040 |
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#define EXTI_FTSR_TR7 0x00000080 |
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#define EXTI_FTSR_TR8 0x00000100 |
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#define EXTI_FTSR_TR9 0x00000200 |
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#define EXTI_FTSR_TR10 0x00000400 |
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#define EXTI_FTSR_TR11 0x00000800 |
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#define EXTI_FTSR_TR12 0x00001000 |
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#define EXTI_FTSR_TR13 0x00002000 |
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#define EXTI_FTSR_TR14 0x00004000 |
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#define EXTI_FTSR_TR15 0x00008000 |
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#define EXTI_FTSR_TR16 0x00010000 |
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#define EXTI_FTSR_TR17 0x00020000 |
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#define EXTI_FTSR_TR18 0x00040000 |
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#define EXTI_FTSR_TR19 0x00080000 |
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#define EXTI_SWIER_SWIER0 0x00000001 |
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#define EXTI_SWIER_SWIER1 0x00000002 |
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#define EXTI_SWIER_SWIER2 0x00000004 |
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#define EXTI_SWIER_SWIER3 0x00000008 |
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#define EXTI_SWIER_SWIER4 0x00000010 |
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#define EXTI_SWIER_SWIER5 0x00000020 |
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#define EXTI_SWIER_SWIER6 0x00000040 |
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#define EXTI_SWIER_SWIER7 0x00000080 |
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#define EXTI_SWIER_SWIER8 0x00000100 |
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#define EXTI_SWIER_SWIER9 0x00000200 |
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#define EXTI_SWIER_SWIER10 0x00000400 |
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#define EXTI_SWIER_SWIER11 0x00000800 |
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#define EXTI_SWIER_SWIER12 0x00001000 |
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#define EXTI_SWIER_SWIER13 0x00002000 |
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#define EXTI_SWIER_SWIER14 0x00004000 |
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#define EXTI_SWIER_SWIER15 0x00008000 |
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#define EXTI_SWIER_SWIER16 0x00010000 |
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#define EXTI_SWIER_SWIER17 0x00020000 |
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#define EXTI_SWIER_SWIER18 0x00040000 |
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#define EXTI_SWIER_SWIER19 0x00080000 |
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#define EXTI_PR_PR0 0x00000001 |
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#define EXTI_PR_PR1 0x00000002 |
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#define EXTI_PR_PR2 0x00000004 |
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#define EXTI_PR_PR3 0x00000008 |
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#define EXTI_PR_PR4 0x00000010 |
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#define EXTI_PR_PR5 0x00000020 |
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#define EXTI_PR_PR6 0x00000040 |
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#define EXTI_PR_PR7 0x00000080 |
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#define EXTI_PR_PR8 0x00000100 |
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#define EXTI_PR_PR9 0x00000200 |
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#define EXTI_PR_PR10 0x00000400 |
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#define EXTI_PR_PR11 0x00000800 |
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#define EXTI_PR_PR12 0x00001000 |
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#define EXTI_PR_PR13 0x00002000 |
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#define EXTI_PR_PR14 0x00004000 |
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#define EXTI_PR_PR15 0x00008000 |
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#define EXTI_PR_PR16 0x00010000 |
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#define EXTI_PR_PR17 0x00020000 |
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#define EXTI_PR_PR18 0x00040000 |
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#define EXTI_PR_PR19 0x00080000 |
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#define EXTI0_IRQ 6 |
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#define EXTI1_IRQ 7 |
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#define EXTI2_IRQ 8 |
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#define EXTI3_IRQ 9 |
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#define EXTI4_IRQ 10 |
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#define EXTI9_5_IRQ 23 |
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#define TIM2_IRQ 28 |
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#define TIM3_IRQ 29 |
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#define TIM4_IRQ 30 |
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struct AFIO |
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{ |
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volatile uint32_t EVCR; |
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volatile uint32_t MAPR; |
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volatile uint32_t EXTICR[4]; |
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uint32_t RESERVED0; |
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volatile uint32_t MAPR2; |
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}; |
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#define AFIO_BASE 0x40010000 |
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static struct AFIO *const AFIO = (struct AFIO *)AFIO_BASE; |
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#define AFIO_EXTICR1_EXTI0_PA 0x0000 |
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#define AFIO_EXTICR1_EXTI0_PB 0x0001 |
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#define AFIO_EXTICR1_EXTI0_PC 0x0002 |
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#define AFIO_EXTICR1_EXTI0_PD 0x0003 |
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#define AFIO_EXTICR1_EXTI1_PA 0x0000 |
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#define AFIO_EXTICR1_EXTI1_PB 0x0010 |
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#define AFIO_EXTICR1_EXTI1_PC 0x0020 |
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#define AFIO_EXTICR1_EXTI1_PD 0x0030 |
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#define AFIO_EXTICR1_EXTI2_PA 0x0000 |
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#define AFIO_EXTICR1_EXTI2_PB 0x0100 |
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#define AFIO_EXTICR1_EXTI2_PC 0x0200 |
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#define AFIO_EXTICR1_EXTI2_PD 0x0300 |
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#define AFIO_EXTICR1_EXTI3_PA 0x0000 |
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#define AFIO_EXTICR1_EXTI3_PB 0x1000 |
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#define AFIO_EXTICR1_EXTI3_PC 0x2000 |
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#define AFIO_EXTICR1_EXTI3_PD 0x3000 |
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#define AFIO_EXTICR2_EXTI4_PA 0x0000 |
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#define AFIO_EXTICR2_EXTI4_PB 0x0001 |
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#define AFIO_EXTICR2_EXTI4_PC 0x0002 |
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#define AFIO_EXTICR2_EXTI4_PD 0x0003 |
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#define AFIO_EXTICR2_EXTI5_PA 0x0000 |
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#define AFIO_EXTICR2_EXTI5_PB 0x0010 |
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#define AFIO_EXTICR2_EXTI5_PC 0x0020 |
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#define AFIO_EXTICR2_EXTI5_PD 0x0030 |
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#define AFIO_EXTICR2_EXTI6_PA 0x0000 |
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#define AFIO_EXTICR2_EXTI6_PB 0x0100 |
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#define AFIO_EXTICR2_EXTI6_PC 0x0200 |
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#define AFIO_EXTICR2_EXTI6_PD 0x0300 |
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#define AFIO_EXTICR2_EXTI7_PA 0x0000 |
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#define AFIO_EXTICR2_EXTI7_PB 0x1000 |
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#define AFIO_EXTICR2_EXTI7_PC 0x2000 |
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#define AFIO_EXTICR2_EXTI7_PD 0x3000 |
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#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP 0x00000800 |
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#define AFIO_MAPR_SWJ_CFG_DISABLE 0x04000000 |
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#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE 0x02000000 |
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struct DBGMCU { |
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volatile uint32_t CR; |
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}; |
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#define DBGMCU_BASE 0xE0042004 |
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#define DBG_SLEEP 1 |
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static struct DBGMCU *const DBGMCU = (struct DBGMCU *)DBGMCU_BASE;
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