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741 lines
19 KiB
741 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2004 Simtec Electronics |
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* Ben Dooks <[email protected]> |
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* |
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* S3C2410 Watchdog Timer Support |
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* |
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* Based on, softdog.c by Alan Cox, |
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* (c) Copyright 1996 Alan Cox <[email protected]> |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/types.h> |
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#include <linux/timer.h> |
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#include <linux/watchdog.h> |
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#include <linux/platform_device.h> |
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#include <linux/interrupt.h> |
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#include <linux/clk.h> |
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#include <linux/uaccess.h> |
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#include <linux/io.h> |
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#include <linux/cpufreq.h> |
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <linux/delay.h> |
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#define S3C2410_WTCON 0x00 |
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#define S3C2410_WTDAT 0x04 |
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#define S3C2410_WTCNT 0x08 |
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#define S3C2410_WTCLRINT 0x0c |
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#define S3C2410_WTCNT_MAXCNT 0xffff |
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#define S3C2410_WTCON_RSTEN (1 << 0) |
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#define S3C2410_WTCON_INTEN (1 << 2) |
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#define S3C2410_WTCON_ENABLE (1 << 5) |
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#define S3C2410_WTCON_DIV16 (0 << 3) |
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#define S3C2410_WTCON_DIV32 (1 << 3) |
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#define S3C2410_WTCON_DIV64 (2 << 3) |
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#define S3C2410_WTCON_DIV128 (3 << 3) |
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#define S3C2410_WTCON_MAXDIV 0x80 |
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#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) |
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#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8) |
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#define S3C2410_WTCON_PRESCALE_MAX 0xff |
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#define S3C2410_WATCHDOG_ATBOOT (0) |
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#define S3C2410_WATCHDOG_DEFAULT_TIME (15) |
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#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 |
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#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 |
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#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c |
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#define QUIRK_HAS_PMU_CONFIG (1 << 0) |
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#define QUIRK_HAS_RST_STAT (1 << 1) |
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#define QUIRK_HAS_WTCLRINT_REG (1 << 2) |
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|
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/* These quirks require that we have a PMU register map */ |
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#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ |
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QUIRK_HAS_RST_STAT) |
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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static int tmr_margin; |
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static int tmr_atboot = S3C2410_WATCHDOG_ATBOOT; |
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static int soft_noboot; |
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module_param(tmr_margin, int, 0); |
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module_param(tmr_atboot, int, 0); |
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module_param(nowayout, bool, 0); |
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module_param(soft_noboot, int, 0); |
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MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default=" |
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__MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")"); |
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MODULE_PARM_DESC(tmr_atboot, |
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"Watchdog is started at boot time if set to 1, default=" |
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__MODULE_STRING(S3C2410_WATCHDOG_ATBOOT)); |
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
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MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)"); |
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/** |
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* struct s3c2410_wdt_variant - Per-variant config data |
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* |
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* @disable_reg: Offset in pmureg for the register that disables the watchdog |
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* timer reset functionality. |
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* @mask_reset_reg: Offset in pmureg for the register that masks the watchdog |
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* timer reset functionality. |
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* @mask_bit: Bit number for the watchdog timer in the disable register and the |
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* mask reset register. |
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* @rst_stat_reg: Offset in pmureg for the register that has the reset status. |
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* @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog |
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* reset. |
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* @quirks: A bitfield of quirks. |
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*/ |
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struct s3c2410_wdt_variant { |
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int disable_reg; |
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int mask_reset_reg; |
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int mask_bit; |
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int rst_stat_reg; |
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int rst_stat_bit; |
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u32 quirks; |
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}; |
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struct s3c2410_wdt { |
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struct device *dev; |
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struct clk *clock; |
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void __iomem *reg_base; |
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unsigned int count; |
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spinlock_t lock; |
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unsigned long wtcon_save; |
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unsigned long wtdat_save; |
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struct watchdog_device wdt_device; |
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struct notifier_block freq_transition; |
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const struct s3c2410_wdt_variant *drv_data; |
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struct regmap *pmureg; |
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}; |
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static const struct s3c2410_wdt_variant drv_data_s3c2410 = { |
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.quirks = 0 |
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}; |
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#ifdef CONFIG_OF |
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static const struct s3c2410_wdt_variant drv_data_s3c6410 = { |
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.quirks = QUIRK_HAS_WTCLRINT_REG, |
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}; |
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static const struct s3c2410_wdt_variant drv_data_exynos5250 = { |
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, |
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, |
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.mask_bit = 20, |
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
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.rst_stat_bit = 20, |
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
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| QUIRK_HAS_WTCLRINT_REG, |
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}; |
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static const struct s3c2410_wdt_variant drv_data_exynos5420 = { |
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, |
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, |
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.mask_bit = 0, |
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
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.rst_stat_bit = 9, |
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
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| QUIRK_HAS_WTCLRINT_REG, |
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}; |
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static const struct s3c2410_wdt_variant drv_data_exynos7 = { |
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, |
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, |
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.mask_bit = 23, |
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, |
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.rst_stat_bit = 23, /* A57 WDTRESET */ |
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \ |
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| QUIRK_HAS_WTCLRINT_REG, |
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}; |
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static const struct of_device_id s3c2410_wdt_match[] = { |
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{ .compatible = "samsung,s3c2410-wdt", |
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.data = &drv_data_s3c2410 }, |
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{ .compatible = "samsung,s3c6410-wdt", |
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.data = &drv_data_s3c6410 }, |
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{ .compatible = "samsung,exynos5250-wdt", |
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.data = &drv_data_exynos5250 }, |
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{ .compatible = "samsung,exynos5420-wdt", |
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.data = &drv_data_exynos5420 }, |
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{ .compatible = "samsung,exynos7-wdt", |
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.data = &drv_data_exynos7 }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); |
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#endif |
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static const struct platform_device_id s3c2410_wdt_ids[] = { |
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{ |
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.name = "s3c2410-wdt", |
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.driver_data = (unsigned long)&drv_data_s3c2410, |
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}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids); |
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|
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/* functions */ |
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static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock) |
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{ |
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unsigned long freq = clk_get_rate(clock); |
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return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1) |
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/ S3C2410_WTCON_MAXDIV); |
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} |
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static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb) |
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{ |
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return container_of(nb, struct s3c2410_wdt, freq_transition); |
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} |
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static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) |
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{ |
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int ret; |
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u32 mask_val = 1 << wdt->drv_data->mask_bit; |
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u32 val = 0; |
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/* No need to do anything if no PMU CONFIG needed */ |
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if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) |
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return 0; |
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if (mask) |
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val = mask_val; |
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ret = regmap_update_bits(wdt->pmureg, |
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wdt->drv_data->disable_reg, |
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mask_val, val); |
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if (ret < 0) |
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goto error; |
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ret = regmap_update_bits(wdt->pmureg, |
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wdt->drv_data->mask_reset_reg, |
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mask_val, val); |
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error: |
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if (ret < 0) |
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dev_err(wdt->dev, "failed to update reg(%d)\n", ret); |
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return ret; |
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} |
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static int s3c2410wdt_keepalive(struct watchdog_device *wdd) |
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{ |
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
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spin_lock(&wdt->lock); |
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writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); |
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spin_unlock(&wdt->lock); |
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return 0; |
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} |
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static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt) |
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{ |
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unsigned long wtcon; |
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wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
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wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); |
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writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
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} |
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static int s3c2410wdt_stop(struct watchdog_device *wdd) |
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{ |
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
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spin_lock(&wdt->lock); |
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__s3c2410wdt_stop(wdt); |
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spin_unlock(&wdt->lock); |
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return 0; |
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} |
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static int s3c2410wdt_start(struct watchdog_device *wdd) |
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{ |
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unsigned long wtcon; |
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
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spin_lock(&wdt->lock); |
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__s3c2410wdt_stop(wdt); |
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wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
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wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; |
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if (soft_noboot) { |
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wtcon |= S3C2410_WTCON_INTEN; |
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wtcon &= ~S3C2410_WTCON_RSTEN; |
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} else { |
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wtcon &= ~S3C2410_WTCON_INTEN; |
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wtcon |= S3C2410_WTCON_RSTEN; |
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} |
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dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n", |
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wdt->count, wtcon); |
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writel(wdt->count, wdt->reg_base + S3C2410_WTDAT); |
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writel(wdt->count, wdt->reg_base + S3C2410_WTCNT); |
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writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
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spin_unlock(&wdt->lock); |
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return 0; |
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} |
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static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt) |
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{ |
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return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE; |
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} |
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static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, |
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unsigned int timeout) |
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{ |
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
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unsigned long freq = clk_get_rate(wdt->clock); |
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unsigned int count; |
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unsigned int divisor = 1; |
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unsigned long wtcon; |
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if (timeout < 1) |
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return -EINVAL; |
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freq = DIV_ROUND_UP(freq, 128); |
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count = timeout * freq; |
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dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n", |
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count, timeout, freq); |
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/* if the count is bigger than the watchdog register, |
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then work out what we need to do (and if) we can |
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actually make this value |
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*/ |
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if (count >= 0x10000) { |
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divisor = DIV_ROUND_UP(count, 0xffff); |
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if (divisor > 0x100) { |
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dev_err(wdt->dev, "timeout %d too big\n", timeout); |
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return -EINVAL; |
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} |
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} |
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dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n", |
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timeout, divisor, count, DIV_ROUND_UP(count, divisor)); |
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count = DIV_ROUND_UP(count, divisor); |
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wdt->count = count; |
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|
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/* update the pre-scaler */ |
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wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
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wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; |
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wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); |
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writel(count, wdt->reg_base + S3C2410_WTDAT); |
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writel(wtcon, wdt->reg_base + S3C2410_WTCON); |
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wdd->timeout = (count * divisor) / freq; |
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return 0; |
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} |
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static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action, |
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void *data) |
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{ |
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); |
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void __iomem *wdt_base = wdt->reg_base; |
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/* disable watchdog, to be safe */ |
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writel(0, wdt_base + S3C2410_WTCON); |
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/* put initial values into count and data */ |
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writel(0x80, wdt_base + S3C2410_WTCNT); |
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writel(0x80, wdt_base + S3C2410_WTDAT); |
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|
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/* set the watchdog to go and reset... */ |
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writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | |
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S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), |
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wdt_base + S3C2410_WTCON); |
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/* wait for reset to assert... */ |
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mdelay(500); |
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return 0; |
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} |
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#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) |
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static const struct watchdog_info s3c2410_wdt_ident = { |
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.options = OPTIONS, |
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.firmware_version = 0, |
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.identity = "S3C2410 Watchdog", |
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}; |
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static const struct watchdog_ops s3c2410wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = s3c2410wdt_start, |
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.stop = s3c2410wdt_stop, |
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.ping = s3c2410wdt_keepalive, |
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.set_timeout = s3c2410wdt_set_heartbeat, |
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.restart = s3c2410wdt_restart, |
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}; |
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static const struct watchdog_device s3c2410_wdd = { |
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.info = &s3c2410_wdt_ident, |
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.ops = &s3c2410wdt_ops, |
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.timeout = S3C2410_WATCHDOG_DEFAULT_TIME, |
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}; |
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|
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/* interrupt handler code */ |
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static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
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{ |
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struct s3c2410_wdt *wdt = platform_get_drvdata(param); |
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dev_info(wdt->dev, "watchdog timer expired (irq)\n"); |
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s3c2410wdt_keepalive(&wdt->wdt_device); |
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|
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if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG) |
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writel(0x1, wdt->reg_base + S3C2410_WTCLRINT); |
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|
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return IRQ_HANDLED; |
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} |
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|
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
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|
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static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb, |
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unsigned long val, void *data) |
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{ |
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int ret; |
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struct s3c2410_wdt *wdt = freq_to_wdt(nb); |
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|
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if (!s3c2410wdt_is_running(wdt)) |
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goto done; |
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|
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if (val == CPUFREQ_PRECHANGE) { |
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/* To ensure that over the change we don't cause the |
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* watchdog to trigger, we perform an keep-alive if |
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* the watchdog is running. |
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*/ |
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|
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s3c2410wdt_keepalive(&wdt->wdt_device); |
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} else if (val == CPUFREQ_POSTCHANGE) { |
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s3c2410wdt_stop(&wdt->wdt_device); |
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|
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ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
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wdt->wdt_device.timeout); |
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|
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if (ret >= 0) |
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s3c2410wdt_start(&wdt->wdt_device); |
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else |
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goto err; |
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} |
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|
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done: |
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return 0; |
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|
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err: |
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dev_err(wdt->dev, "cannot set new value for timeout %d\n", |
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wdt->wdt_device.timeout); |
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return ret; |
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} |
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|
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static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
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{ |
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wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
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|
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return cpufreq_register_notifier(&wdt->freq_transition, |
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CPUFREQ_TRANSITION_NOTIFIER); |
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} |
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|
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static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
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{ |
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wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition; |
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|
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cpufreq_unregister_notifier(&wdt->freq_transition, |
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CPUFREQ_TRANSITION_NOTIFIER); |
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} |
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|
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#else |
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|
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static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt) |
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{ |
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return 0; |
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} |
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|
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static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) |
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{ |
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} |
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#endif |
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|
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static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) |
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{ |
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unsigned int rst_stat; |
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int ret; |
|
|
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if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) |
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return 0; |
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|
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ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); |
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if (ret) |
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dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); |
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else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) |
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return WDIOF_CARDRESET; |
|
|
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return 0; |
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} |
|
|
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static inline const struct s3c2410_wdt_variant * |
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s3c2410_get_wdt_drv_data(struct platform_device *pdev) |
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{ |
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const struct s3c2410_wdt_variant *variant; |
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|
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variant = of_device_get_match_data(&pdev->dev); |
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if (!variant) { |
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/* Device matched by platform_device_id */ |
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variant = (struct s3c2410_wdt_variant *) |
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platform_get_device_id(pdev)->driver_data; |
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} |
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|
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return variant; |
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} |
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|
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static int s3c2410wdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct s3c2410_wdt *wdt; |
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struct resource *wdt_irq; |
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unsigned int wtcon; |
|
int started = 0; |
|
int ret; |
|
|
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
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if (!wdt) |
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return -ENOMEM; |
|
|
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wdt->dev = dev; |
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spin_lock_init(&wdt->lock); |
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wdt->wdt_device = s3c2410_wdd; |
|
|
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wdt->drv_data = s3c2410_get_wdt_drv_data(pdev); |
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if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { |
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wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, |
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"samsung,syscon-phandle"); |
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if (IS_ERR(wdt->pmureg)) { |
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dev_err(dev, "syscon regmap lookup failed.\n"); |
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return PTR_ERR(wdt->pmureg); |
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} |
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} |
|
|
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wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
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if (wdt_irq == NULL) { |
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dev_err(dev, "no irq resource specified\n"); |
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ret = -ENOENT; |
|
goto err; |
|
} |
|
|
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/* get the memory region for the watchdog timer */ |
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wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(wdt->reg_base)) { |
|
ret = PTR_ERR(wdt->reg_base); |
|
goto err; |
|
} |
|
|
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wdt->clock = devm_clk_get(dev, "watchdog"); |
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if (IS_ERR(wdt->clock)) { |
|
dev_err(dev, "failed to find watchdog clock source\n"); |
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ret = PTR_ERR(wdt->clock); |
|
goto err; |
|
} |
|
|
|
ret = clk_prepare_enable(wdt->clock); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to enable clock\n"); |
|
return ret; |
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} |
|
|
|
wdt->wdt_device.min_timeout = 1; |
|
wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock); |
|
|
|
ret = s3c2410wdt_cpufreq_register(wdt); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to register cpufreq\n"); |
|
goto err_clk; |
|
} |
|
|
|
watchdog_set_drvdata(&wdt->wdt_device, wdt); |
|
|
|
/* see if we can actually set the requested timer margin, and if |
|
* not, try the default value */ |
|
|
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watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev); |
|
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
|
wdt->wdt_device.timeout); |
|
if (ret) { |
|
started = s3c2410wdt_set_heartbeat(&wdt->wdt_device, |
|
S3C2410_WATCHDOG_DEFAULT_TIME); |
|
|
|
if (started == 0) |
|
dev_info(dev, |
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"tmr_margin value out of range, default %d used\n", |
|
S3C2410_WATCHDOG_DEFAULT_TIME); |
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else |
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dev_info(dev, "default timer value is out of range, cannot start\n"); |
|
} |
|
|
|
ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0, |
|
pdev->name, pdev); |
|
if (ret != 0) { |
|
dev_err(dev, "failed to install irq (%d)\n", ret); |
|
goto err_cpufreq; |
|
} |
|
|
|
watchdog_set_nowayout(&wdt->wdt_device, nowayout); |
|
watchdog_set_restart_priority(&wdt->wdt_device, 128); |
|
|
|
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); |
|
wdt->wdt_device.parent = dev; |
|
|
|
ret = watchdog_register_device(&wdt->wdt_device); |
|
if (ret) |
|
goto err_cpufreq; |
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
|
if (ret < 0) |
|
goto err_unregister; |
|
|
|
if (tmr_atboot && started == 0) { |
|
dev_info(dev, "starting watchdog timer\n"); |
|
s3c2410wdt_start(&wdt->wdt_device); |
|
} else if (!tmr_atboot) { |
|
/* if we're not enabling the watchdog, then ensure it is |
|
* disabled if it has been left running from the bootloader |
|
* or other source */ |
|
|
|
s3c2410wdt_stop(&wdt->wdt_device); |
|
} |
|
|
|
platform_set_drvdata(pdev, wdt); |
|
|
|
/* print out a statement of readiness */ |
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON); |
|
|
|
dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
|
(wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
|
(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis", |
|
(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis"); |
|
|
|
return 0; |
|
|
|
err_unregister: |
|
watchdog_unregister_device(&wdt->wdt_device); |
|
|
|
err_cpufreq: |
|
s3c2410wdt_cpufreq_deregister(wdt); |
|
|
|
err_clk: |
|
clk_disable_unprepare(wdt->clock); |
|
|
|
err: |
|
return ret; |
|
} |
|
|
|
static int s3c2410wdt_remove(struct platform_device *dev) |
|
{ |
|
int ret; |
|
struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
|
if (ret < 0) |
|
return ret; |
|
|
|
watchdog_unregister_device(&wdt->wdt_device); |
|
|
|
s3c2410wdt_cpufreq_deregister(wdt); |
|
|
|
clk_disable_unprepare(wdt->clock); |
|
|
|
return 0; |
|
} |
|
|
|
static void s3c2410wdt_shutdown(struct platform_device *dev) |
|
{ |
|
struct s3c2410_wdt *wdt = platform_get_drvdata(dev); |
|
|
|
s3c2410wdt_mask_and_disable_reset(wdt, true); |
|
|
|
s3c2410wdt_stop(&wdt->wdt_device); |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
|
|
static int s3c2410wdt_suspend(struct device *dev) |
|
{ |
|
int ret; |
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
|
|
|
/* Save watchdog state, and turn it off. */ |
|
wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON); |
|
wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT); |
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, true); |
|
if (ret < 0) |
|
return ret; |
|
|
|
/* Note that WTCNT doesn't need to be saved. */ |
|
s3c2410wdt_stop(&wdt->wdt_device); |
|
|
|
return 0; |
|
} |
|
|
|
static int s3c2410wdt_resume(struct device *dev) |
|
{ |
|
int ret; |
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev); |
|
|
|
/* Restore watchdog state. */ |
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT); |
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */ |
|
writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON); |
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, false); |
|
if (ret < 0) |
|
return ret; |
|
|
|
dev_info(dev, "watchdog %sabled\n", |
|
(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend, |
|
s3c2410wdt_resume); |
|
|
|
static struct platform_driver s3c2410wdt_driver = { |
|
.probe = s3c2410wdt_probe, |
|
.remove = s3c2410wdt_remove, |
|
.shutdown = s3c2410wdt_shutdown, |
|
.id_table = s3c2410_wdt_ids, |
|
.driver = { |
|
.name = "s3c2410-wdt", |
|
.pm = &s3c2410wdt_pm_ops, |
|
.of_match_table = of_match_ptr(s3c2410_wdt_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(s3c2410wdt_driver); |
|
|
|
MODULE_AUTHOR("Ben Dooks <[email protected]>, Dimitry Andric <[email protected]>"); |
|
MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|