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347 lines
8.6 KiB
347 lines
8.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Watchdog driver for Renesas WDT watchdog |
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* |
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* Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <[email protected]> |
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* Copyright (C) 2015-17 Renesas Electronics Corporation |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/smp.h> |
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#include <linux/sys_soc.h> |
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#include <linux/watchdog.h> |
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#define RWTCNT 0 |
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#define RWTCSRA 4 |
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#define RWTCSRA_WOVF BIT(4) |
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#define RWTCSRA_WRFLG BIT(5) |
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#define RWTCSRA_TME BIT(7) |
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#define RWTCSRB 8 |
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#define RWDT_DEFAULT_TIMEOUT 60U |
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/* |
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* In probe, clk_rate is checked to be not more than 16 bit * biggest clock |
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* divider (12 bits). d is only a factor to fully utilize the WDT counter and |
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* will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits. |
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*/ |
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#define MUL_BY_CLKS_PER_SEC(p, d) \ |
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DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks]) |
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/* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */ |
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#define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate) |
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static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 }; |
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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module_param(nowayout, bool, 0); |
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
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struct rwdt_priv { |
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void __iomem *base; |
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struct watchdog_device wdev; |
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unsigned long clk_rate; |
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u8 cks; |
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struct clk *clk; |
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}; |
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static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg) |
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{ |
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if (reg == RWTCNT) |
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val |= 0x5a5a0000; |
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else |
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val |= 0xa5a5a500; |
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writel_relaxed(val, priv->base + reg); |
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} |
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static int rwdt_init_timeout(struct watchdog_device *wdev) |
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{ |
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struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
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rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); |
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return 0; |
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} |
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static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles) |
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{ |
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unsigned int delay; |
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delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); |
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usleep_range(delay, 2 * delay); |
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} |
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static int rwdt_start(struct watchdog_device *wdev) |
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{ |
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struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
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u8 val; |
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pm_runtime_get_sync(wdev->parent); |
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/* Stop the timer before we modify any register */ |
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val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME; |
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rwdt_write(priv, val, RWTCSRA); |
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/* Delay 2 cycles before setting watchdog counter */ |
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rwdt_wait_cycles(priv, 2); |
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rwdt_init_timeout(wdev); |
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rwdt_write(priv, priv->cks, RWTCSRA); |
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rwdt_write(priv, 0, RWTCSRB); |
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while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG) |
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cpu_relax(); |
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rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA); |
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return 0; |
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} |
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static int rwdt_stop(struct watchdog_device *wdev) |
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{ |
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struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
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rwdt_write(priv, priv->cks, RWTCSRA); |
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/* Delay 3 cycles before disabling module clock */ |
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rwdt_wait_cycles(priv, 3); |
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pm_runtime_put(wdev->parent); |
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return 0; |
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} |
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static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev) |
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{ |
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struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
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u16 val = readw_relaxed(priv->base + RWTCNT); |
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return DIV_BY_CLKS_PER_SEC(priv, 65536 - val); |
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} |
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/* needs to be atomic - no RPM, no usleep_range, no scheduling! */ |
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static int rwdt_restart(struct watchdog_device *wdev, unsigned long action, |
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void *data) |
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{ |
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struct rwdt_priv *priv = watchdog_get_drvdata(wdev); |
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u8 val; |
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clk_prepare_enable(priv->clk); |
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/* Stop the timer before we modify any register */ |
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val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME; |
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rwdt_write(priv, val, RWTCSRA); |
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/* Delay 2 cycles before setting watchdog counter */ |
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udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate)); |
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rwdt_write(priv, 0xffff, RWTCNT); |
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/* smallest divider to reboot soon */ |
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rwdt_write(priv, 0, RWTCSRA); |
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readb_poll_timeout_atomic(priv->base + RWTCSRA, val, |
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!(val & RWTCSRA_WRFLG), 1, 100); |
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rwdt_write(priv, RWTCSRA_TME, RWTCSRA); |
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/* wait 2 cycles, so watchdog will trigger */ |
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udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate)); |
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return 0; |
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} |
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static const struct watchdog_info rwdt_ident = { |
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.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
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WDIOF_CARDRESET, |
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.identity = "Renesas WDT Watchdog", |
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}; |
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static const struct watchdog_ops rwdt_ops = { |
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.owner = THIS_MODULE, |
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.start = rwdt_start, |
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.stop = rwdt_stop, |
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.ping = rwdt_init_timeout, |
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.get_timeleft = rwdt_get_timeleft, |
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.restart = rwdt_restart, |
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}; |
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#if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP) |
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/* |
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* Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs |
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*/ |
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static const struct soc_device_attribute rwdt_quirks_match[] = { |
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{ |
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.soc_id = "r8a7790", |
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.revision = "ES1.*", |
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.data = (void *)1, /* needs single CPU */ |
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}, { |
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.soc_id = "r8a7791", |
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.revision = "ES1.*", |
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.data = (void *)1, /* needs single CPU */ |
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}, { |
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.soc_id = "r8a7792", |
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.data = (void *)0, /* needs SMP disabled */ |
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}, |
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{ /* sentinel */ } |
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}; |
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static bool rwdt_blacklisted(struct device *dev) |
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{ |
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const struct soc_device_attribute *attr; |
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attr = soc_device_match(rwdt_quirks_match); |
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if (attr && setup_max_cpus > (uintptr_t)attr->data) { |
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dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id, |
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attr->revision); |
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return true; |
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} |
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return false; |
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} |
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#else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */ |
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static inline bool rwdt_blacklisted(struct device *dev) { return false; } |
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#endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */ |
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static int rwdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct rwdt_priv *priv; |
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unsigned long clks_per_sec; |
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int ret, i; |
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u8 csra; |
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if (rwdt_blacklisted(dev)) |
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return -ENODEV; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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priv->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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pm_runtime_enable(dev); |
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pm_runtime_get_sync(dev); |
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priv->clk_rate = clk_get_rate(priv->clk); |
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csra = readb_relaxed(priv->base + RWTCSRA); |
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priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0; |
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pm_runtime_put(dev); |
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if (!priv->clk_rate) { |
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ret = -ENOENT; |
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goto out_pm_disable; |
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} |
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for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) { |
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clks_per_sec = priv->clk_rate / clk_divs[i]; |
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if (clks_per_sec && clks_per_sec < 65536) { |
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priv->cks = i; |
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break; |
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} |
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} |
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if (i < 0) { |
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dev_err(dev, "Can't find suitable clock divider\n"); |
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ret = -ERANGE; |
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goto out_pm_disable; |
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} |
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priv->wdev.info = &rwdt_ident; |
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priv->wdev.ops = &rwdt_ops; |
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priv->wdev.parent = dev; |
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priv->wdev.min_timeout = 1; |
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priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536); |
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priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT); |
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platform_set_drvdata(pdev, priv); |
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watchdog_set_drvdata(&priv->wdev, priv); |
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watchdog_set_nowayout(&priv->wdev, nowayout); |
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watchdog_set_restart_priority(&priv->wdev, 0); |
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watchdog_stop_on_unregister(&priv->wdev); |
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/* This overrides the default timeout only if DT configuration was found */ |
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watchdog_init_timeout(&priv->wdev, 0, dev); |
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/* Check if FW enabled the watchdog */ |
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if (csra & RWTCSRA_TME) { |
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/* Ensure properly initialized dividers */ |
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rwdt_start(&priv->wdev); |
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set_bit(WDOG_HW_RUNNING, &priv->wdev.status); |
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} |
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ret = watchdog_register_device(&priv->wdev); |
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if (ret < 0) |
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goto out_pm_disable; |
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return 0; |
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out_pm_disable: |
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pm_runtime_disable(dev); |
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return ret; |
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} |
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static int rwdt_remove(struct platform_device *pdev) |
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{ |
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struct rwdt_priv *priv = platform_get_drvdata(pdev); |
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watchdog_unregister_device(&priv->wdev); |
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pm_runtime_disable(&pdev->dev); |
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return 0; |
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} |
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static int __maybe_unused rwdt_suspend(struct device *dev) |
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{ |
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struct rwdt_priv *priv = dev_get_drvdata(dev); |
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if (watchdog_active(&priv->wdev)) |
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rwdt_stop(&priv->wdev); |
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return 0; |
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} |
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static int __maybe_unused rwdt_resume(struct device *dev) |
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{ |
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struct rwdt_priv *priv = dev_get_drvdata(dev); |
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if (watchdog_active(&priv->wdev)) |
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rwdt_start(&priv->wdev); |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume); |
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static const struct of_device_id rwdt_ids[] = { |
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{ .compatible = "renesas,rcar-gen2-wdt", }, |
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{ .compatible = "renesas,rcar-gen3-wdt", }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, rwdt_ids); |
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static struct platform_driver rwdt_driver = { |
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.driver = { |
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.name = "renesas_wdt", |
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.of_match_table = rwdt_ids, |
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.pm = &rwdt_pm_ops, |
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}, |
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.probe = rwdt_probe, |
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.remove = rwdt_remove, |
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}; |
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module_platform_driver(rwdt_driver); |
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MODULE_DESCRIPTION("Renesas WDT Watchdog Driver"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_AUTHOR("Wolfram Sang <[email protected]>");
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