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310 lines
7.2 KiB
310 lines
7.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright 2019 NXP. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/reboot.h> |
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#include <linux/watchdog.h> |
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#define WDOG_CS 0x0 |
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#define WDOG_CS_CMD32EN BIT(13) |
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#define WDOG_CS_ULK BIT(11) |
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#define WDOG_CS_RCS BIT(10) |
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#define LPO_CLK 0x1 |
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#define LPO_CLK_SHIFT 8 |
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#define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT) |
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#define WDOG_CS_EN BIT(7) |
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#define WDOG_CS_UPDATE BIT(5) |
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#define WDOG_CS_WAIT BIT(1) |
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#define WDOG_CS_STOP BIT(0) |
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#define WDOG_CNT 0x4 |
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#define WDOG_TOVAL 0x8 |
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#define REFRESH_SEQ0 0xA602 |
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#define REFRESH_SEQ1 0xB480 |
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#define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0) |
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#define UNLOCK_SEQ0 0xC520 |
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#define UNLOCK_SEQ1 0xD928 |
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#define UNLOCK ((UNLOCK_SEQ1 << 16) | UNLOCK_SEQ0) |
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#define DEFAULT_TIMEOUT 60 |
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#define MAX_TIMEOUT 128 |
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#define WDOG_CLOCK_RATE 1000 |
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#define WDOG_WAIT_TIMEOUT 20 |
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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module_param(nowayout, bool, 0000); |
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
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struct imx7ulp_wdt_device { |
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struct watchdog_device wdd; |
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void __iomem *base; |
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struct clk *clk; |
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}; |
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static int imx7ulp_wdt_wait(void __iomem *base, u32 mask) |
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{ |
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u32 val = readl(base + WDOG_CS); |
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if (!(val & mask) && readl_poll_timeout_atomic(base + WDOG_CS, val, |
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val & mask, 0, |
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WDOG_WAIT_TIMEOUT)) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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static int imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable) |
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{ |
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); |
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u32 val = readl(wdt->base + WDOG_CS); |
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int ret; |
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local_irq_disable(); |
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writel(UNLOCK, wdt->base + WDOG_CNT); |
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ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); |
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if (ret) |
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goto enable_out; |
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if (enable) |
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writel(val | WDOG_CS_EN, wdt->base + WDOG_CS); |
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else |
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writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS); |
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imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS); |
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enable_out: |
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local_irq_enable(); |
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return ret; |
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} |
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static bool imx7ulp_wdt_is_enabled(void __iomem *base) |
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{ |
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u32 val = readl(base + WDOG_CS); |
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return val & WDOG_CS_EN; |
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} |
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static int imx7ulp_wdt_ping(struct watchdog_device *wdog) |
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{ |
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); |
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writel(REFRESH, wdt->base + WDOG_CNT); |
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return 0; |
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} |
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static int imx7ulp_wdt_start(struct watchdog_device *wdog) |
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{ |
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return imx7ulp_wdt_enable(wdog, true); |
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} |
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static int imx7ulp_wdt_stop(struct watchdog_device *wdog) |
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{ |
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return imx7ulp_wdt_enable(wdog, false); |
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} |
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static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog, |
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unsigned int timeout) |
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{ |
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); |
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u32 val = WDOG_CLOCK_RATE * timeout; |
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int ret; |
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local_irq_disable(); |
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writel(UNLOCK, wdt->base + WDOG_CNT); |
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ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); |
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if (ret) |
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goto timeout_out; |
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writel(val, wdt->base + WDOG_TOVAL); |
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imx7ulp_wdt_wait(wdt->base, WDOG_CS_RCS); |
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wdog->timeout = timeout; |
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timeout_out: |
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local_irq_enable(); |
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return ret; |
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} |
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static int imx7ulp_wdt_restart(struct watchdog_device *wdog, |
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unsigned long action, void *data) |
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{ |
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struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog); |
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int ret; |
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ret = imx7ulp_wdt_enable(wdog, true); |
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if (ret) |
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return ret; |
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ret = imx7ulp_wdt_set_timeout(&wdt->wdd, 1); |
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if (ret) |
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return ret; |
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/* wait for wdog to fire */ |
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while (true) |
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; |
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return NOTIFY_DONE; |
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} |
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static const struct watchdog_ops imx7ulp_wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = imx7ulp_wdt_start, |
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.stop = imx7ulp_wdt_stop, |
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.ping = imx7ulp_wdt_ping, |
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.set_timeout = imx7ulp_wdt_set_timeout, |
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.restart = imx7ulp_wdt_restart, |
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}; |
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static const struct watchdog_info imx7ulp_wdt_info = { |
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.identity = "i.MX7ULP watchdog timer", |
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | |
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WDIOF_MAGICCLOSE, |
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}; |
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static int imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) |
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{ |
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u32 val; |
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int ret; |
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local_irq_disable(); |
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/* unlock the wdog for reconfiguration */ |
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writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT); |
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writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT); |
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ret = imx7ulp_wdt_wait(base, WDOG_CS_ULK); |
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if (ret) |
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goto init_out; |
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/* set an initial timeout value in TOVAL */ |
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writel(timeout, base + WDOG_TOVAL); |
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/* enable 32bit command sequence and reconfigure */ |
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val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE | |
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WDOG_CS_WAIT | WDOG_CS_STOP; |
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writel(val, base + WDOG_CS); |
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imx7ulp_wdt_wait(base, WDOG_CS_RCS); |
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init_out: |
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local_irq_enable(); |
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return ret; |
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} |
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static void imx7ulp_wdt_action(void *data) |
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{ |
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clk_disable_unprepare(data); |
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} |
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static int imx7ulp_wdt_probe(struct platform_device *pdev) |
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{ |
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struct imx7ulp_wdt_device *imx7ulp_wdt; |
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struct device *dev = &pdev->dev; |
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struct watchdog_device *wdog; |
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int ret; |
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imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL); |
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if (!imx7ulp_wdt) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, imx7ulp_wdt); |
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imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(imx7ulp_wdt->base)) |
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return PTR_ERR(imx7ulp_wdt->base); |
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imx7ulp_wdt->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(imx7ulp_wdt->clk)) { |
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dev_err(dev, "Failed to get watchdog clock\n"); |
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return PTR_ERR(imx7ulp_wdt->clk); |
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} |
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ret = clk_prepare_enable(imx7ulp_wdt->clk); |
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if (ret) |
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return ret; |
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ret = devm_add_action_or_reset(dev, imx7ulp_wdt_action, imx7ulp_wdt->clk); |
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if (ret) |
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return ret; |
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wdog = &imx7ulp_wdt->wdd; |
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wdog->info = &imx7ulp_wdt_info; |
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wdog->ops = &imx7ulp_wdt_ops; |
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wdog->min_timeout = 1; |
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wdog->max_timeout = MAX_TIMEOUT; |
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wdog->parent = dev; |
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wdog->timeout = DEFAULT_TIMEOUT; |
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watchdog_init_timeout(wdog, 0, dev); |
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watchdog_stop_on_reboot(wdog); |
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watchdog_stop_on_unregister(wdog); |
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watchdog_set_drvdata(wdog, imx7ulp_wdt); |
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ret = imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE); |
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if (ret) |
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return ret; |
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return devm_watchdog_register_device(dev, wdog); |
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} |
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static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev) |
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{ |
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struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev); |
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if (watchdog_active(&imx7ulp_wdt->wdd)) |
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imx7ulp_wdt_stop(&imx7ulp_wdt->wdd); |
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clk_disable_unprepare(imx7ulp_wdt->clk); |
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return 0; |
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} |
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static int __maybe_unused imx7ulp_wdt_resume(struct device *dev) |
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{ |
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struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev); |
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u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE; |
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int ret; |
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ret = clk_prepare_enable(imx7ulp_wdt->clk); |
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if (ret) |
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return ret; |
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if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base)) |
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imx7ulp_wdt_init(imx7ulp_wdt->base, timeout); |
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if (watchdog_active(&imx7ulp_wdt->wdd)) |
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imx7ulp_wdt_start(&imx7ulp_wdt->wdd); |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops, imx7ulp_wdt_suspend, |
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imx7ulp_wdt_resume); |
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static const struct of_device_id imx7ulp_wdt_dt_ids[] = { |
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{ .compatible = "fsl,imx7ulp-wdt", }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids); |
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static struct platform_driver imx7ulp_wdt_driver = { |
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.probe = imx7ulp_wdt_probe, |
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.driver = { |
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.name = "imx7ulp-wdt", |
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.pm = &imx7ulp_wdt_pm_ops, |
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.of_match_table = imx7ulp_wdt_dt_ids, |
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}, |
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}; |
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module_platform_driver(imx7ulp_wdt_driver); |
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MODULE_AUTHOR("Anson Huang <[email protected]>"); |
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MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver"); |
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MODULE_LICENSE("GPL v2");
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