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721 lines
19 KiB
721 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2010-2011 Picochip Ltd., Jamie Iles |
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* https://www.picochip.com |
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* |
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* This file implements a driver for the Synopsys DesignWare watchdog device |
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* in the many subsystems. The watchdog has 16 different timeout periods |
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* and these are a function of the input clock frequency. |
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* |
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* The DesignWare watchdog cannot be stopped once it has been started so we |
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* do not implement a stop function. The watchdog core will continue to send |
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* heartbeat requests after the watchdog device has been closed. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/debugfs.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/limits.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm.h> |
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#include <linux/reset.h> |
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#include <linux/watchdog.h> |
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#define WDOG_CONTROL_REG_OFFSET 0x00 |
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#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 |
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#define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02 |
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#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 |
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#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 |
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#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 |
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#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c |
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#define WDOG_COUNTER_RESTART_KICK_VALUE 0x76 |
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#define WDOG_INTERRUPT_STATUS_REG_OFFSET 0x10 |
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#define WDOG_INTERRUPT_CLEAR_REG_OFFSET 0x14 |
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#define WDOG_COMP_PARAMS_5_REG_OFFSET 0xe4 |
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#define WDOG_COMP_PARAMS_4_REG_OFFSET 0xe8 |
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#define WDOG_COMP_PARAMS_3_REG_OFFSET 0xec |
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#define WDOG_COMP_PARAMS_2_REG_OFFSET 0xf0 |
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#define WDOG_COMP_PARAMS_1_REG_OFFSET 0xf4 |
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#define WDOG_COMP_PARAMS_1_USE_FIX_TOP BIT(6) |
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#define WDOG_COMP_VERSION_REG_OFFSET 0xf8 |
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#define WDOG_COMP_TYPE_REG_OFFSET 0xfc |
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/* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */ |
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#define DW_WDT_NUM_TOPS 16 |
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#define DW_WDT_FIX_TOP(_idx) (1U << (16 + _idx)) |
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#define DW_WDT_DEFAULT_SECONDS 30 |
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static const u32 dw_wdt_fix_tops[DW_WDT_NUM_TOPS] = { |
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DW_WDT_FIX_TOP(0), DW_WDT_FIX_TOP(1), DW_WDT_FIX_TOP(2), |
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DW_WDT_FIX_TOP(3), DW_WDT_FIX_TOP(4), DW_WDT_FIX_TOP(5), |
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DW_WDT_FIX_TOP(6), DW_WDT_FIX_TOP(7), DW_WDT_FIX_TOP(8), |
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DW_WDT_FIX_TOP(9), DW_WDT_FIX_TOP(10), DW_WDT_FIX_TOP(11), |
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DW_WDT_FIX_TOP(12), DW_WDT_FIX_TOP(13), DW_WDT_FIX_TOP(14), |
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DW_WDT_FIX_TOP(15) |
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}; |
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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module_param(nowayout, bool, 0); |
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
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"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
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enum dw_wdt_rmod { |
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DW_WDT_RMOD_RESET = 1, |
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DW_WDT_RMOD_IRQ = 2 |
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}; |
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struct dw_wdt_timeout { |
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u32 top_val; |
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unsigned int sec; |
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unsigned int msec; |
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}; |
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struct dw_wdt { |
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void __iomem *regs; |
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struct clk *clk; |
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struct clk *pclk; |
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unsigned long rate; |
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enum dw_wdt_rmod rmod; |
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struct dw_wdt_timeout timeouts[DW_WDT_NUM_TOPS]; |
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struct watchdog_device wdd; |
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struct reset_control *rst; |
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/* Save/restore */ |
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u32 control; |
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u32 timeout; |
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#ifdef CONFIG_DEBUG_FS |
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struct dentry *dbgfs_dir; |
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#endif |
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}; |
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#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) |
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static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt) |
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{ |
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return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) & |
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WDOG_CONTROL_REG_WDT_EN_MASK; |
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} |
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static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod) |
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{ |
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u32 val; |
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val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
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if (rmod == DW_WDT_RMOD_IRQ) |
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val |= WDOG_CONTROL_REG_RESP_MODE_MASK; |
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else |
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val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; |
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writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
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dw_wdt->rmod = rmod; |
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} |
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static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt, |
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unsigned int timeout, u32 *top_val) |
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{ |
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int idx; |
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/* |
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* Find a TOP with timeout greater or equal to the requested number. |
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* Note we'll select a TOP with maximum timeout if the requested |
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* timeout couldn't be reached. |
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*/ |
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for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) { |
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if (dw_wdt->timeouts[idx].sec >= timeout) |
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break; |
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} |
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if (idx == DW_WDT_NUM_TOPS) |
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--idx; |
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*top_val = dw_wdt->timeouts[idx].top_val; |
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return dw_wdt->timeouts[idx].sec; |
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} |
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static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt) |
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{ |
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int idx; |
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/* |
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* We'll find a timeout greater or equal to one second anyway because |
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* the driver probe would have failed if there was none. |
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*/ |
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for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) { |
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if (dw_wdt->timeouts[idx].sec) |
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break; |
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} |
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return dw_wdt->timeouts[idx].sec; |
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} |
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static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt) |
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{ |
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struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1]; |
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u64 msec; |
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msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec; |
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return msec < UINT_MAX ? msec : UINT_MAX; |
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} |
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static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt) |
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{ |
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int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF; |
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int idx; |
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for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) { |
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if (dw_wdt->timeouts[idx].top_val == top_val) |
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break; |
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} |
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/* |
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* In IRQ mode due to the two stages counter, the actual timeout is |
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* twice greater than the TOP setting. |
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*/ |
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return dw_wdt->timeouts[idx].sec * dw_wdt->rmod; |
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} |
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static int dw_wdt_ping(struct watchdog_device *wdd) |
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{ |
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
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writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + |
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WDOG_COUNTER_RESTART_REG_OFFSET); |
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return 0; |
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} |
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static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) |
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{ |
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
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unsigned int timeout; |
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u32 top_val; |
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/* |
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* Note IRQ mode being enabled means having a non-zero pre-timeout |
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* setup. In this case we try to find a TOP as close to the half of the |
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* requested timeout as possible since DW Watchdog IRQ mode is designed |
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* in two stages way - first timeout rises the pre-timeout interrupt, |
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* second timeout performs the system reset. So basically the effective |
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* watchdog-caused reset happens after two watchdog TOPs elapsed. |
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*/ |
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timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod), |
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&top_val); |
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if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) |
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wdd->pretimeout = timeout; |
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else |
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wdd->pretimeout = 0; |
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/* |
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* Set the new value in the watchdog. Some versions of dw_wdt |
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* have have TOPINIT in the TIMEOUT_RANGE register (as per |
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* CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we |
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* effectively get a pat of the watchdog right here. |
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*/ |
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writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, |
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dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
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/* Kick new TOP value into the watchdog counter if activated. */ |
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if (watchdog_active(wdd)) |
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dw_wdt_ping(wdd); |
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/* |
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* In case users set bigger timeout value than HW can support, |
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* kernel(watchdog_dev.c) helps to feed watchdog before |
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* wdd->max_hw_heartbeat_ms |
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*/ |
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if (top_s * 1000 <= wdd->max_hw_heartbeat_ms) |
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wdd->timeout = timeout * dw_wdt->rmod; |
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else |
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wdd->timeout = top_s; |
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return 0; |
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} |
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static int dw_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req) |
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{ |
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
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/* |
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* We ignore actual value of the timeout passed from user-space |
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* using it as a flag whether the pretimeout functionality is intended |
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* to be activated. |
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*/ |
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dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET); |
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dw_wdt_set_timeout(wdd, wdd->timeout); |
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return 0; |
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} |
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static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt) |
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{ |
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u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
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/* Disable/enable interrupt mode depending on the RMOD flag. */ |
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if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) |
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val |= WDOG_CONTROL_REG_RESP_MODE_MASK; |
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else |
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val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; |
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/* Enable watchdog. */ |
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val |= WDOG_CONTROL_REG_WDT_EN_MASK; |
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writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
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} |
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static int dw_wdt_start(struct watchdog_device *wdd) |
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{ |
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
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dw_wdt_set_timeout(wdd, wdd->timeout); |
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dw_wdt_ping(&dw_wdt->wdd); |
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dw_wdt_arm_system_reset(dw_wdt); |
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return 0; |
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} |
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static int dw_wdt_stop(struct watchdog_device *wdd) |
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{ |
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
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if (!dw_wdt->rst) { |
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set_bit(WDOG_HW_RUNNING, &wdd->status); |
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return 0; |
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} |
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reset_control_assert(dw_wdt->rst); |
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reset_control_deassert(dw_wdt->rst); |
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return 0; |
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} |
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static int dw_wdt_restart(struct watchdog_device *wdd, |
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unsigned long action, void *data) |
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{ |
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
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writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
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dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET); |
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if (dw_wdt_is_enabled(dw_wdt)) |
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writel(WDOG_COUNTER_RESTART_KICK_VALUE, |
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dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); |
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else |
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dw_wdt_arm_system_reset(dw_wdt); |
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/* wait for reset to assert... */ |
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mdelay(500); |
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return 0; |
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} |
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static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd) |
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{ |
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
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unsigned int sec; |
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u32 val; |
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val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET); |
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sec = val / dw_wdt->rate; |
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if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) { |
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val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET); |
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if (!val) |
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sec += wdd->pretimeout; |
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} |
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return sec; |
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} |
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static const struct watchdog_info dw_wdt_ident = { |
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
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WDIOF_MAGICCLOSE, |
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.identity = "Synopsys DesignWare Watchdog", |
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}; |
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static const struct watchdog_info dw_wdt_pt_ident = { |
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | |
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WDIOF_PRETIMEOUT | WDIOF_MAGICCLOSE, |
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.identity = "Synopsys DesignWare Watchdog", |
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}; |
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static const struct watchdog_ops dw_wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = dw_wdt_start, |
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.stop = dw_wdt_stop, |
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.ping = dw_wdt_ping, |
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.set_timeout = dw_wdt_set_timeout, |
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.set_pretimeout = dw_wdt_set_pretimeout, |
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.get_timeleft = dw_wdt_get_timeleft, |
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.restart = dw_wdt_restart, |
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}; |
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static irqreturn_t dw_wdt_irq(int irq, void *devid) |
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{ |
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struct dw_wdt *dw_wdt = devid; |
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u32 val; |
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/* |
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* We don't clear the IRQ status. It's supposed to be done by the |
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* following ping operations. |
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*/ |
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val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET); |
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if (!val) |
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return IRQ_NONE; |
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watchdog_notify_pretimeout(&dw_wdt->wdd); |
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return IRQ_HANDLED; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int dw_wdt_suspend(struct device *dev) |
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{ |
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struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
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dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
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dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
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clk_disable_unprepare(dw_wdt->pclk); |
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clk_disable_unprepare(dw_wdt->clk); |
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return 0; |
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} |
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static int dw_wdt_resume(struct device *dev) |
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{ |
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struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
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int err = clk_prepare_enable(dw_wdt->clk); |
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if (err) |
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return err; |
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err = clk_prepare_enable(dw_wdt->pclk); |
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if (err) { |
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clk_disable_unprepare(dw_wdt->clk); |
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return err; |
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} |
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writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
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writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
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dw_wdt_ping(&dw_wdt->wdd); |
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return 0; |
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} |
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#endif /* CONFIG_PM_SLEEP */ |
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static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); |
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/* |
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* In case if DW WDT IP core is synthesized with fixed TOP feature disabled the |
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* TOPs array can be arbitrary ordered with nearly any sixteen uint numbers |
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* depending on the system engineer imagination. The next method handles the |
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* passed TOPs array to pre-calculate the effective timeouts and to sort the |
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* TOP items out in the ascending order with respect to the timeouts. |
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*/ |
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static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops) |
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{ |
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struct dw_wdt_timeout tout, *dst; |
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int val, tidx; |
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u64 msec; |
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/* |
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* We walk over the passed TOPs array and calculate corresponding |
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* timeouts in seconds and milliseconds. The milliseconds granularity |
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* is needed to distinguish the TOPs with very close timeouts and to |
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* set the watchdog max heartbeat setting further. |
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*/ |
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for (val = 0; val < DW_WDT_NUM_TOPS; ++val) { |
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tout.top_val = val; |
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tout.sec = tops[val] / dw_wdt->rate; |
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msec = (u64)tops[val] * MSEC_PER_SEC; |
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do_div(msec, dw_wdt->rate); |
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tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC); |
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/* |
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* Find a suitable place for the current TOP in the timeouts |
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* array so that the list is remained in the ascending order. |
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*/ |
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for (tidx = 0; tidx < val; ++tidx) { |
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dst = &dw_wdt->timeouts[tidx]; |
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if (tout.sec > dst->sec || (tout.sec == dst->sec && |
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tout.msec >= dst->msec)) |
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continue; |
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else |
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swap(*dst, tout); |
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} |
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dw_wdt->timeouts[val] = tout; |
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} |
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} |
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static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev) |
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{ |
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u32 data, of_tops[DW_WDT_NUM_TOPS]; |
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const u32 *tops; |
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int ret; |
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|
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/* |
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* Retrieve custom or fixed counter values depending on the |
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* WDT_USE_FIX_TOP flag found in the component specific parameters |
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* #1 register. |
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*/ |
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data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET); |
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if (data & WDOG_COMP_PARAMS_1_USE_FIX_TOP) { |
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tops = dw_wdt_fix_tops; |
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} else { |
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ret = of_property_read_variable_u32_array(dev_of_node(dev), |
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"snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS, |
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DW_WDT_NUM_TOPS); |
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if (ret < 0) { |
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dev_warn(dev, "No valid TOPs array specified\n"); |
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tops = dw_wdt_fix_tops; |
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} else { |
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tops = of_tops; |
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} |
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} |
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/* Convert the specified TOPs into an array of watchdog timeouts. */ |
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dw_wdt_handle_tops(dw_wdt, tops); |
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if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) { |
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dev_err(dev, "No any valid TOP detected\n"); |
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return -EINVAL; |
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} |
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|
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return 0; |
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} |
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#ifdef CONFIG_DEBUG_FS |
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|
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#define DW_WDT_DBGFS_REG(_name, _off) \ |
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{ \ |
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.name = _name, \ |
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.offset = _off \ |
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} |
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|
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static const struct debugfs_reg32 dw_wdt_dbgfs_regs[] = { |
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DW_WDT_DBGFS_REG("cr", WDOG_CONTROL_REG_OFFSET), |
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DW_WDT_DBGFS_REG("torr", WDOG_TIMEOUT_RANGE_REG_OFFSET), |
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DW_WDT_DBGFS_REG("ccvr", WDOG_CURRENT_COUNT_REG_OFFSET), |
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DW_WDT_DBGFS_REG("crr", WDOG_COUNTER_RESTART_REG_OFFSET), |
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DW_WDT_DBGFS_REG("stat", WDOG_INTERRUPT_STATUS_REG_OFFSET), |
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DW_WDT_DBGFS_REG("param5", WDOG_COMP_PARAMS_5_REG_OFFSET), |
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DW_WDT_DBGFS_REG("param4", WDOG_COMP_PARAMS_4_REG_OFFSET), |
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DW_WDT_DBGFS_REG("param3", WDOG_COMP_PARAMS_3_REG_OFFSET), |
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DW_WDT_DBGFS_REG("param2", WDOG_COMP_PARAMS_2_REG_OFFSET), |
|
DW_WDT_DBGFS_REG("param1", WDOG_COMP_PARAMS_1_REG_OFFSET), |
|
DW_WDT_DBGFS_REG("version", WDOG_COMP_VERSION_REG_OFFSET), |
|
DW_WDT_DBGFS_REG("type", WDOG_COMP_TYPE_REG_OFFSET) |
|
}; |
|
|
|
static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) |
|
{ |
|
struct device *dev = dw_wdt->wdd.parent; |
|
struct debugfs_regset32 *regset; |
|
|
|
regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); |
|
if (!regset) |
|
return; |
|
|
|
regset->regs = dw_wdt_dbgfs_regs; |
|
regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs); |
|
regset->base = dw_wdt->regs; |
|
|
|
dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL); |
|
|
|
debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset); |
|
} |
|
|
|
static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) |
|
{ |
|
debugfs_remove_recursive(dw_wdt->dbgfs_dir); |
|
} |
|
|
|
#else /* !CONFIG_DEBUG_FS */ |
|
|
|
static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {} |
|
static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {} |
|
|
|
#endif /* !CONFIG_DEBUG_FS */ |
|
|
|
static int dw_wdt_drv_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct watchdog_device *wdd; |
|
struct dw_wdt *dw_wdt; |
|
int ret; |
|
|
|
dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL); |
|
if (!dw_wdt) |
|
return -ENOMEM; |
|
|
|
dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(dw_wdt->regs)) |
|
return PTR_ERR(dw_wdt->regs); |
|
|
|
/* |
|
* Try to request the watchdog dedicated timer clock source. It must |
|
* be supplied if asynchronous mode is enabled. Otherwise fallback |
|
* to the common timer/bus clocks configuration, in which the very |
|
* first found clock supply both timer and APB signals. |
|
*/ |
|
dw_wdt->clk = devm_clk_get(dev, "tclk"); |
|
if (IS_ERR(dw_wdt->clk)) { |
|
dw_wdt->clk = devm_clk_get(dev, NULL); |
|
if (IS_ERR(dw_wdt->clk)) |
|
return PTR_ERR(dw_wdt->clk); |
|
} |
|
|
|
ret = clk_prepare_enable(dw_wdt->clk); |
|
if (ret) |
|
return ret; |
|
|
|
dw_wdt->rate = clk_get_rate(dw_wdt->clk); |
|
if (dw_wdt->rate == 0) { |
|
ret = -EINVAL; |
|
goto out_disable_clk; |
|
} |
|
|
|
/* |
|
* Request APB clock if device is configured with async clocks mode. |
|
* In this case both tclk and pclk clocks are supposed to be specified. |
|
* Alas we can't know for sure whether async mode was really activated, |
|
* so the pclk phandle reference is left optional. If it couldn't be |
|
* found we consider the device configured in synchronous clocks mode. |
|
*/ |
|
dw_wdt->pclk = devm_clk_get_optional(dev, "pclk"); |
|
if (IS_ERR(dw_wdt->pclk)) { |
|
ret = PTR_ERR(dw_wdt->pclk); |
|
goto out_disable_clk; |
|
} |
|
|
|
ret = clk_prepare_enable(dw_wdt->pclk); |
|
if (ret) |
|
goto out_disable_clk; |
|
|
|
dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); |
|
if (IS_ERR(dw_wdt->rst)) { |
|
ret = PTR_ERR(dw_wdt->rst); |
|
goto out_disable_pclk; |
|
} |
|
|
|
/* Enable normal reset without pre-timeout by default. */ |
|
dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET); |
|
|
|
/* |
|
* Pre-timeout IRQ is optional, since some hardware may lack support |
|
* of it. Note we must request rising-edge IRQ, since the lane is left |
|
* pending either until the next watchdog kick event or up to the |
|
* system reset. |
|
*/ |
|
ret = platform_get_irq_optional(pdev, 0); |
|
if (ret > 0) { |
|
ret = devm_request_irq(dev, ret, dw_wdt_irq, |
|
IRQF_SHARED | IRQF_TRIGGER_RISING, |
|
pdev->name, dw_wdt); |
|
if (ret) |
|
goto out_disable_pclk; |
|
|
|
dw_wdt->wdd.info = &dw_wdt_pt_ident; |
|
} else { |
|
if (ret == -EPROBE_DEFER) |
|
goto out_disable_pclk; |
|
|
|
dw_wdt->wdd.info = &dw_wdt_ident; |
|
} |
|
|
|
reset_control_deassert(dw_wdt->rst); |
|
|
|
ret = dw_wdt_init_timeouts(dw_wdt, dev); |
|
if (ret) |
|
goto out_disable_clk; |
|
|
|
wdd = &dw_wdt->wdd; |
|
wdd->ops = &dw_wdt_ops; |
|
wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt); |
|
wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt); |
|
wdd->parent = dev; |
|
|
|
watchdog_set_drvdata(wdd, dw_wdt); |
|
watchdog_set_nowayout(wdd, nowayout); |
|
watchdog_init_timeout(wdd, 0, dev); |
|
|
|
/* |
|
* If the watchdog is already running, use its already configured |
|
* timeout. Otherwise use the default or the value provided through |
|
* devicetree. |
|
*/ |
|
if (dw_wdt_is_enabled(dw_wdt)) { |
|
wdd->timeout = dw_wdt_get_timeout(dw_wdt); |
|
set_bit(WDOG_HW_RUNNING, &wdd->status); |
|
} else { |
|
wdd->timeout = DW_WDT_DEFAULT_SECONDS; |
|
watchdog_init_timeout(wdd, 0, dev); |
|
} |
|
|
|
platform_set_drvdata(pdev, dw_wdt); |
|
|
|
watchdog_set_restart_priority(wdd, 128); |
|
|
|
ret = watchdog_register_device(wdd); |
|
if (ret) |
|
goto out_disable_pclk; |
|
|
|
dw_wdt_dbgfs_init(dw_wdt); |
|
|
|
return 0; |
|
|
|
out_disable_pclk: |
|
clk_disable_unprepare(dw_wdt->pclk); |
|
|
|
out_disable_clk: |
|
clk_disable_unprepare(dw_wdt->clk); |
|
return ret; |
|
} |
|
|
|
static int dw_wdt_drv_remove(struct platform_device *pdev) |
|
{ |
|
struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); |
|
|
|
dw_wdt_dbgfs_clear(dw_wdt); |
|
|
|
watchdog_unregister_device(&dw_wdt->wdd); |
|
reset_control_assert(dw_wdt->rst); |
|
clk_disable_unprepare(dw_wdt->pclk); |
|
clk_disable_unprepare(dw_wdt->clk); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id dw_wdt_of_match[] = { |
|
{ .compatible = "snps,dw-wdt", }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, dw_wdt_of_match); |
|
#endif |
|
|
|
static struct platform_driver dw_wdt_driver = { |
|
.probe = dw_wdt_drv_probe, |
|
.remove = dw_wdt_drv_remove, |
|
.driver = { |
|
.name = "dw_wdt", |
|
.of_match_table = of_match_ptr(dw_wdt_of_match), |
|
.pm = &dw_wdt_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(dw_wdt_driver); |
|
|
|
MODULE_AUTHOR("Jamie Iles"); |
|
MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|