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405 lines
11 KiB
405 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2016 IBM Corporation |
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* |
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* Joel Stanley <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/watchdog.h> |
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struct aspeed_wdt { |
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struct watchdog_device wdd; |
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void __iomem *base; |
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u32 ctrl; |
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}; |
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struct aspeed_wdt_config { |
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u32 ext_pulse_width_mask; |
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}; |
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static const struct aspeed_wdt_config ast2400_config = { |
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.ext_pulse_width_mask = 0xff, |
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}; |
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static const struct aspeed_wdt_config ast2500_config = { |
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.ext_pulse_width_mask = 0xfffff, |
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}; |
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static const struct of_device_id aspeed_wdt_of_table[] = { |
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{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config }, |
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{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config }, |
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{ .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); |
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#define WDT_STATUS 0x00 |
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#define WDT_RELOAD_VALUE 0x04 |
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#define WDT_RESTART 0x08 |
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#define WDT_CTRL 0x0C |
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#define WDT_CTRL_BOOT_SECONDARY BIT(7) |
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#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) |
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#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) |
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#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) |
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#define WDT_CTRL_1MHZ_CLK BIT(4) |
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#define WDT_CTRL_WDT_EXT BIT(3) |
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#define WDT_CTRL_WDT_INTR BIT(2) |
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#define WDT_CTRL_RESET_SYSTEM BIT(1) |
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#define WDT_CTRL_ENABLE BIT(0) |
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#define WDT_TIMEOUT_STATUS 0x10 |
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#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) |
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#define WDT_CLEAR_TIMEOUT_STATUS 0x14 |
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#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) |
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/* |
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* WDT_RESET_WIDTH controls the characteristics of the external pulse (if |
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* enabled), specifically: |
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* |
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* * Pulse duration |
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* * Drive mode: push-pull vs open-drain |
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* * Polarity: Active high or active low |
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* |
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* Pulse duration configuration is available on both the AST2400 and AST2500, |
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* though the field changes between SoCs: |
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* |
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* AST2400: Bits 7:0 |
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* AST2500: Bits 19:0 |
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* |
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* This difference is captured in struct aspeed_wdt_config. |
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* |
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* The AST2500 exposes the drive mode and polarity options, but not in a |
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* regular fashion. For read purposes, bit 31 represents active high or low, |
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* and bit 30 represents push-pull or open-drain. With respect to write, magic |
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* values need to be written to the top byte to change the state of the drive |
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* mode and polarity bits. Any other value written to the top byte has no |
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* effect on the state of the drive mode or polarity bits. However, the pulse |
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* width value must be preserved (as desired) if written. |
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*/ |
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#define WDT_RESET_WIDTH 0x18 |
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#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) |
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#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) |
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#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) |
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#define WDT_RESET_WIDTH_PUSH_PULL BIT(30) |
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#define WDT_PUSH_PULL_MAGIC (0xA8 << 24) |
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#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) |
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#define WDT_RESTART_MAGIC 0x4755 |
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/* 32 bits at 1MHz, in milliseconds */ |
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#define WDT_MAX_TIMEOUT_MS 4294967 |
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#define WDT_DEFAULT_TIMEOUT 30 |
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#define WDT_RATE_1MHZ 1000000 |
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static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd) |
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{ |
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return container_of(wdd, struct aspeed_wdt, wdd); |
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} |
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static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count) |
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{ |
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wdt->ctrl |= WDT_CTRL_ENABLE; |
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writel(0, wdt->base + WDT_CTRL); |
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writel(count, wdt->base + WDT_RELOAD_VALUE); |
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writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); |
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writel(wdt->ctrl, wdt->base + WDT_CTRL); |
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} |
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static int aspeed_wdt_start(struct watchdog_device *wdd) |
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{ |
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); |
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aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ); |
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return 0; |
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} |
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static int aspeed_wdt_stop(struct watchdog_device *wdd) |
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{ |
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); |
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wdt->ctrl &= ~WDT_CTRL_ENABLE; |
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writel(wdt->ctrl, wdt->base + WDT_CTRL); |
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return 0; |
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} |
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static int aspeed_wdt_ping(struct watchdog_device *wdd) |
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{ |
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); |
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writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); |
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return 0; |
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} |
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static int aspeed_wdt_set_timeout(struct watchdog_device *wdd, |
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unsigned int timeout) |
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{ |
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); |
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u32 actual; |
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wdd->timeout = timeout; |
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actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000); |
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writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); |
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writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); |
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return 0; |
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} |
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static int aspeed_wdt_restart(struct watchdog_device *wdd, |
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unsigned long action, void *data) |
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{ |
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struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); |
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wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY; |
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aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000); |
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mdelay(1000); |
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return 0; |
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} |
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/* access_cs0 shows if cs0 is accessible, hence the reverted bit */ |
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static ssize_t access_cs0_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct aspeed_wdt *wdt = dev_get_drvdata(dev); |
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u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS); |
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return sprintf(buf, "%u\n", |
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!(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)); |
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} |
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static ssize_t access_cs0_store(struct device *dev, |
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struct device_attribute *attr, const char *buf, |
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size_t size) |
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{ |
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struct aspeed_wdt *wdt = dev_get_drvdata(dev); |
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unsigned long val; |
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if (kstrtoul(buf, 10, &val)) |
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return -EINVAL; |
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if (val) |
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writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION, |
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wdt->base + WDT_CLEAR_TIMEOUT_STATUS); |
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return size; |
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} |
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/* |
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* This attribute exists only if the system has booted from the alternate |
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* flash with 'alt-boot' option. |
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* |
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* At alternate flash the 'access_cs0' sysfs node provides: |
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* ast2400: a way to get access to the primary SPI flash chip at CS0 |
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* after booting from the alternate chip at CS1. |
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* ast2500: a way to restore the normal address mapping from |
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* (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1). |
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* |
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* Clearing the boot code selection and timeout counter also resets to the |
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* initial state the chip select line mapping. When the SoC is in normal |
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* mapping state (i.e. booted from CS0), clearing those bits does nothing for |
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* both versions of the SoC. For alternate boot mode (booted from CS1 due to |
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* wdt2 expiration) the behavior differs as described above. |
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* |
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* This option can be used with wdt2 (watchdog1) only. |
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*/ |
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static DEVICE_ATTR_RW(access_cs0); |
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static struct attribute *bswitch_attrs[] = { |
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&dev_attr_access_cs0.attr, |
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NULL |
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}; |
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ATTRIBUTE_GROUPS(bswitch); |
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static const struct watchdog_ops aspeed_wdt_ops = { |
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.start = aspeed_wdt_start, |
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.stop = aspeed_wdt_stop, |
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.ping = aspeed_wdt_ping, |
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.set_timeout = aspeed_wdt_set_timeout, |
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.restart = aspeed_wdt_restart, |
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.owner = THIS_MODULE, |
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}; |
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static const struct watchdog_info aspeed_wdt_info = { |
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.options = WDIOF_KEEPALIVEPING |
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| WDIOF_MAGICCLOSE |
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| WDIOF_SETTIMEOUT, |
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.identity = KBUILD_MODNAME, |
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}; |
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static int aspeed_wdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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const struct aspeed_wdt_config *config; |
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const struct of_device_id *ofdid; |
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struct aspeed_wdt *wdt; |
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struct device_node *np; |
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const char *reset_type; |
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u32 duration; |
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u32 status; |
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int ret; |
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
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if (!wdt) |
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return -ENOMEM; |
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wdt->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(wdt->base)) |
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return PTR_ERR(wdt->base); |
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wdt->wdd.info = &aspeed_wdt_info; |
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wdt->wdd.ops = &aspeed_wdt_ops; |
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wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; |
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wdt->wdd.parent = dev; |
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wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; |
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watchdog_init_timeout(&wdt->wdd, 0, dev); |
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np = dev->of_node; |
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ofdid = of_match_node(aspeed_wdt_of_table, np); |
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if (!ofdid) |
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return -EINVAL; |
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config = ofdid->data; |
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/* |
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* On clock rates: |
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* - ast2400 wdt can run at PCLK, or 1MHz |
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* - ast2500 only runs at 1MHz, hard coding bit 4 to 1 |
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* - ast2600 always runs at 1MHz |
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* |
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* Set the ast2400 to run at 1MHz as it simplifies the driver. |
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*/ |
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if (of_device_is_compatible(np, "aspeed,ast2400-wdt")) |
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wdt->ctrl = WDT_CTRL_1MHZ_CLK; |
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/* |
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* Control reset on a per-device basis to ensure the |
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* host is not affected by a BMC reboot |
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*/ |
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ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); |
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if (ret) { |
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; |
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} else { |
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if (!strcmp(reset_type, "cpu")) |
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wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU | |
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WDT_CTRL_RESET_SYSTEM; |
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else if (!strcmp(reset_type, "soc")) |
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | |
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WDT_CTRL_RESET_SYSTEM; |
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else if (!strcmp(reset_type, "system")) |
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wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP | |
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WDT_CTRL_RESET_SYSTEM; |
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else if (strcmp(reset_type, "none")) |
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return -EINVAL; |
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} |
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if (of_property_read_bool(np, "aspeed,external-signal")) |
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wdt->ctrl |= WDT_CTRL_WDT_EXT; |
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if (of_property_read_bool(np, "aspeed,alt-boot")) |
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wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY; |
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if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { |
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/* |
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* The watchdog is running, but invoke aspeed_wdt_start() to |
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* write wdt->ctrl to WDT_CTRL to ensure the watchdog's |
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* configuration conforms to the driver's expectations. |
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* Primarily, ensure we're using the 1MHz clock source. |
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*/ |
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aspeed_wdt_start(&wdt->wdd); |
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set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); |
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} |
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if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) || |
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(of_device_is_compatible(np, "aspeed,ast2600-wdt"))) { |
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u32 reg = readl(wdt->base + WDT_RESET_WIDTH); |
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reg &= config->ext_pulse_width_mask; |
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if (of_property_read_bool(np, "aspeed,ext-push-pull")) |
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reg |= WDT_PUSH_PULL_MAGIC; |
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else |
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reg |= WDT_OPEN_DRAIN_MAGIC; |
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writel(reg, wdt->base + WDT_RESET_WIDTH); |
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reg &= config->ext_pulse_width_mask; |
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if (of_property_read_bool(np, "aspeed,ext-active-high")) |
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reg |= WDT_ACTIVE_HIGH_MAGIC; |
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else |
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reg |= WDT_ACTIVE_LOW_MAGIC; |
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writel(reg, wdt->base + WDT_RESET_WIDTH); |
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} |
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if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) { |
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u32 max_duration = config->ext_pulse_width_mask + 1; |
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if (duration == 0 || duration > max_duration) { |
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dev_err(dev, "Invalid pulse duration: %uus\n", |
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duration); |
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duration = max(1U, min(max_duration, duration)); |
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dev_info(dev, "Pulse duration set to %uus\n", |
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duration); |
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} |
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/* |
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* The watchdog is always configured with a 1MHz source, so |
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* there is no need to scale the microsecond value. However we |
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* need to offset it - from the datasheet: |
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* |
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* "This register decides the asserting duration of wdt_ext and |
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* wdt_rstarm signal. The default value is 0xFF. It means the |
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* default asserting duration of wdt_ext and wdt_rstarm is |
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* 256us." |
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* |
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* This implies a value of 0 gives a 1us pulse. |
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*/ |
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writel(duration - 1, wdt->base + WDT_RESET_WIDTH); |
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} |
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status = readl(wdt->base + WDT_TIMEOUT_STATUS); |
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if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) { |
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wdt->wdd.bootstatus = WDIOF_CARDRESET; |
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if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || |
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of_device_is_compatible(np, "aspeed,ast2500-wdt")) |
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wdt->wdd.groups = bswitch_groups; |
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} |
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dev_set_drvdata(dev, wdt); |
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return devm_watchdog_register_device(dev, &wdt->wdd); |
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} |
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static struct platform_driver aspeed_watchdog_driver = { |
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.probe = aspeed_wdt_probe, |
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.driver = { |
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.name = KBUILD_MODNAME, |
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.of_match_table = of_match_ptr(aspeed_wdt_of_table), |
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}, |
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}; |
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static int __init aspeed_wdt_init(void) |
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{ |
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return platform_driver_register(&aspeed_watchdog_driver); |
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} |
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arch_initcall(aspeed_wdt_init); |
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static void __exit aspeed_wdt_exit(void) |
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{ |
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platform_driver_unregister(&aspeed_watchdog_driver); |
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} |
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module_exit(aspeed_wdt_exit); |
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MODULE_DESCRIPTION("Aspeed Watchdog Driver"); |
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MODULE_LICENSE("GPL");
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